Anki Deck Changes

Commit: 624367e9 - fix some lolo fuckers

Author: obrhubr <obrhubr@gmail.com>

Date: 2026-03-02T15:50:11+01:00

Changes: 10 note(s) changed (3 added, 7 modified, 0 deleted)

ℹ️ Cosmetic Changes Hidden: 1 note(s) had formatting-only changes and are not shown below

Note 1: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Occlusio
GUID: e}`+YBit[=
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ETH::2._Semester::A&W::1._Graphentheorie::5._Kreise::2._Hamiltonkreise
image-occlusion:rect:left=.185:top=.3015:width=.5356:height=.2727:oi=1
image-occlusion:rect:left=.1834:top=.5902:width=.8127:height=.365:oi=1

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ETH::2._Semester::A&W::1._Graphentheorie::5._Kreise::2._Hamiltonkreise
image-occlusion:rect:left=.185:top=.3015:width=.5356:height=.2727:oi=1
image-occlusion:rect:left=.1834:top=.5902:width=.8127:height=.365:oi=1
Field-by-field Comparison
Field Before After
Occlusion {{c1::image-occlusion:rect:left=.185:top=.3015:width=.5356:height=.2727:oi=1}}<br>{{c2::image-occlusion:rect:left=.1834:top=.5902:width=.8127:height=.365:oi=1}}<br>
Image <img src="paste-58c8522fa35a336ff842fea7bd9c0c4bc1289935.jpg">
Tags: ETH::2._Semester::A&W::1._Graphentheorie::5._Kreise::2._Hamiltonkreise

Note 2: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: AG/0U&~#@P
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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
\(N\) locations require \(\log_2 N\) address bits. 

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
\(N\) locations require \(\log_2 N\) address bits. 
 log[#locations]
Field-by-field Comparison
Field Before After
Text \(N\)&nbsp;locations require {{c1::\(\log_2 N\)}} address bits.&nbsp;
Extra &nbsp;log[#locations]
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

Note 3: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: D[owgbdJ
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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::14._Register
What is this?

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::14._Register
What is this?

Here we have a register, or a structure that stores more than one bit and can be read from and written to.

Note that there is a single WE signal for all latches for simultaneous writes.

This register holds 4 bits, and its data is referenced as Q[3:0].

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::14._Register
What is this?

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::14._Register
What is this?

Here we have a register.
  • It's a structure that stores more than one bit and can be read from and written to.
  • Note that there is a single WE signal for all latches for simultaneous writes.
  • This register holds 4 bits, and its data is referenced as Q[3:0].
Field-by-field Comparison
Field Before After
Back Here we have a register, or a structure that stores more than one bit and can be read from and written to.<br><br>Note that there is a single WE signal for all latches for simultaneous writes.<br><br>This register holds 4 bits, and its data is referenced as Q[3:0]. Here we have a <b>register.</b><br><ul><li>It's a structure that stores more than one bit and can be read from and written to.</li><li>Note that there is a single WE signal for all latches for simultaneous writes.</li><li>This register holds 4 bits, and its data is referenced as Q[3:0].</li></ul>
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::14._Register

Note 4: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: J}Cp1R>RJL
modified

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::16._Aside:_Implementing_Logic_Functions_Using_Memory
What is this functionally?

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::16._Aside:_Implementing_Logic_Functions_Using_Memory
What is this functionally?

A memory-bassed lookup table.

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::16._Aside:_Implementing_Logic_Functions_Using_Memory
What is this functionally?

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::16._Aside:_Implementing_Logic_Functions_Using_Memory
What is this functionally?

A memory-based lookup table.
Field-by-field Comparison
Field Before After
Back A memory-bassed lookup table. A memory-based lookup table.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::16._Aside:_Implementing_Logic_Functions_Using_Memory

Note 5: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: g-~*^Ki!(:
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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer
Imagine a wire connecting the CPU and memory. At any time only the CPU or the memory can place a value on the wire, both not both.

How do we model this as a circuit?

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer
Imagine a wire connecting the CPU and memory. At any time only the CPU or the memory can place a value on the wire, both not both.

How do we model this as a circuit?
 You can have two tri-state buffers: one driven by CPU, the other memory; and ensure at most one is enabled at any time.

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer
How do we model a BUS as a circuit?

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer
How do we model a BUS as a circuit?
You can have two tri-state buffers: one driven by CPU, the other memory; and ensure at most one is enabled at any time.

Field-by-field Comparison
Field Before After
Front Imagine a wire connecting the CPU and memory. At any time only the CPU or the memory can place a value on the wire, both not both.<br><br>How do we model this as a circuit? How do we model a BUS as a circuit?
Back &nbsp;You can have two tri-state buffers: one driven by CPU, the other memory; and ensure at most one is enabled at any time.<br><br><img src="paste-3e60268fdf3d3d4e9613807017fd11ee2dd4909f.jpg"> You can have two tri-state buffers: one driven by CPU, the other memory; and ensure at most one is enabled at any time.<br><br><img src="paste-3e60268fdf3d3d4e9613807017fd11ee2dd4909f.jpg">
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer

Note 6: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: vK&i;bo$O;
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ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
MOS transistors are imperfect switches.

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ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
MOS transistors are imperfect switches.
pMOS transistors pass I's well but 0's poorly (holes carry charge).
nMOS transistors pass 0's well but I's poorly (electrons carry charge).

This is why AND is built with NAND + NOT.

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ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
MOS transistors are imperfect switches.
  • pMOS transistors pass I's well but 's poorly (holes carry charge).
  • nMOS transistors pass 0's well but I's poorly (electrons carry charge).

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ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
MOS transistors are imperfect switches.
  • pMOS transistors pass I's well but 's poorly (holes carry charge).
  • nMOS transistors pass 0's well but I's poorly (electrons carry charge).
This is why AND is built with NAND + NOT.
Field-by-field Comparison
Field Before After
Text MOS transistors are {{c1::imperfect}} switches. MOS transistors are imperfect switches.<br><ul><li>pMOS transistors pass {{c1::I}}'s well but {{c10}}'s poorly {{c1::(holes carry&nbsp;charge)}}.</li><li>nMOS transistors pass {{c1::0}}'s well but {{c1::I}}'s poorly {{c1::(electrons carry&nbsp;charge)}}.</li></ul>
Extra pMOS transistors pass I's well but 0's poorly (holes carry&nbsp;charge).<br>nMOS transistors pass 0's well but I's poorly (electrons carry&nbsp;charge).<br><br>This is why AND is built with NAND + NOT. This is why AND is built with NAND + NOT.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 7: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: yixUKU?m~)
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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
Essence of Simplification

Find two-element subsets of the ON-set where only one variable changes its value. This single varying variable can be eliminated!

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
Essence of Simplification

Find two-element subsets of the ON-set where only one variable changes its value. This single varying variable can be eliminated!

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
Essence of Simplification (Uniting Theorem)

Find two-element subsets of the ON-set where only one variable changes its value. This single varying variable can be eliminated!

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
Essence of Simplification (Uniting Theorem)

Find two-element subsets of the ON-set where only one variable changes its value. This single varying variable can be eliminated!
Field-by-field Comparison
Field Before After
Text Essence of Simplification<br><br>Find two-element subsets of the ON-set where only one variable changes its value. This single varying variable can be {{c1::eliminated}}! Essence of Simplification (Uniting Theorem)<br><br>Find two-element subsets of the ON-set where only one variable changes its value. This single varying variable can be {{c1::eliminated}}!
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules

Note 8: ETH::2. Semester::PProg

Deck: ETH::2. Semester::PProg
Note Type: Horvath Cloze
GUID: d%A(hxXDuk
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ETH::2._Semester::PProg::03._Java_Threads
The execution order is non-deterministic.

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ETH::2._Semester::PProg::03._Java_Threads
The execution order is non-deterministic.

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ETH::2._Semester::PProg::03._Java_Threads
The execution order is non-deterministic.

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ETH::2._Semester::PProg::03._Java_Threads
The execution order is non-deterministic.
The OS-Scheduler depends on all currently running processes.
Field-by-field Comparison
Field Before After
Extra The OS-Scheduler depends on all currently running processes.
Tags: ETH::2._Semester::PProg::03._Java_Threads

Note 9: ETH::2. Semester::PProg

Deck: ETH::2. Semester::PProg
Note Type: Horvath Cloze
GUID: w&_kd{VSwY
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ETH::2._Semester::PProg::03._Java_Threads
A critical section is a section of code that must be executed by only one thread or process at a time because it accesses shared resources.

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ETH::2._Semester::PProg::03._Java_Threads
A critical section is a section of code that must be executed by only one thread or process at a time because it accesses shared resources.
Ex: IO, file writing/reading, incrementing global counter
Field-by-field Comparison
Field Before After
Text A critical section is {{c1::a&nbsp;section of code that must be executed by only one thread or process at a time because it accesses shared resources}}.
Extra Ex: IO, file writing/reading, incrementing global counter
Tags: ETH::2._Semester::PProg::03._Java_Threads
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