Anki Deck Changes

Commit: b5c46d7b - off to new ddca horizons..

Author: lhorva <lhorva@student.ethz.ch>

Date: 2026-05-31T22:47:50+02:00

Changes: 322 note(s) changed (80 added, 103 modified, 139 deleted)

ℹ️ Cosmetic Changes Hidden: 62 note(s) had formatting-only changes and are not shown below • 9 HTML formatting changes • 2 mixed cosmetic changes

Note 1: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: +N@/D$lVm_
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ETH::2._Semester::A&W::2._Wahrscheinlichkeitstheorie_und_randomisierte_Algorithmen::8._Randomisierte_Algorithmen::2._Sortieren_und_Selektieren
Selektionsproblem: Bestimme in einer Folge \((A[1], \ldots, A[n])\) paarweise verschiedener Zahlen den \(k\)-kleinsten Wert.

Naiver Ansatz: Sortieren + Index, Laufzeit \(O(n \log n)\).

Schneller geht es mit QuickSelect (erwartet \(O(n)\)):
QuickSelect(A, ℓ, r, k):
  p ← Uniform({ℓ, ℓ+1, ..., r})
  t ← Partition(A, ℓ, r, p)
  if t = ℓ + k - 1: return A[t]    # gefunden
  else if t > ℓ + k - 1:
    return QuickSelect(A, ℓ, t-1, k)     # links
  else:
    return QuickSelect(A, t+1, r, k - t) # rechts

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ETH::2._Semester::A&W::2._Wahrscheinlichkeitstheorie_und_randomisierte_Algorithmen::8._Randomisierte_Algorithmen::2._Sortieren_und_Selektieren
Selektionsproblem: Bestimme in einer Folge \((A[1], \ldots, A[n])\) paarweise verschiedener Zahlen den \(k\)-kleinsten Wert.

Naiver Ansatz: Sortieren + Index, Laufzeit \(O(n \log n)\).

Schneller geht es mit QuickSelect (erwartet \(O(n)\)):
QuickSelect(A, ℓ, r, k):
  p ← Uniform({ℓ, ℓ+1, ..., r})
  t ← Partition(A, ℓ, r, p)
  if t = ℓ + k - 1: return A[t]    # gefunden
  else if t > ℓ + k - 1:
    return QuickSelect(A, ℓ, t-1, k)     # links
  else:
    return QuickSelect(A, t+1, r, k - t) # rechts

Im Gegensatz zu QuickSort rekursiert QuickSelect nur in eine der beiden Hälften (oder gibt direkt zurück, falls Pivot bereits an der gesuchten Position liegt). Das macht den Unterschied zwischen \(O(n \log n)\) und \(O(n)\) erwartet.

Bei einem Aufruf von QuickSelect ist die Anzahl Vergleiche \(T = \sum_{i=1}^{N} (r_i - \ell_i)\), wobei \(N\) die Anzahl Partition-Aufrufe ist.

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ETH::2._Semester::A&W::2._Wahrscheinlichkeitstheorie_und_randomisierte_Algorithmen::8._Randomisierte_Algorithmen::2._Sortieren_und_Selektieren
Selektionsproblem: Bestimme in einer Folge \((A[1], \ldots, A[n])\) paarweise verschiedener Zahlen den \(k\)-kleinsten Wert.

Naiver Ansatz: Sortieren + Index, Laufzeit \(O(n \log n)\).

Schneller geht es mit QuickSelect (erwartet \(O(n)\)):

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ETH::2._Semester::A&W::2._Wahrscheinlichkeitstheorie_und_randomisierte_Algorithmen::8._Randomisierte_Algorithmen::2._Sortieren_und_Selektieren
Selektionsproblem: Bestimme in einer Folge \((A[1], \ldots, A[n])\) paarweise verschiedener Zahlen den \(k\)-kleinsten Wert.

Naiver Ansatz: Sortieren + Index, Laufzeit \(O(n \log n)\).

Schneller geht es mit QuickSelect (erwartet \(O(n)\)):


Im Gegensatz zu QuickSort rekursiert QuickSelect nur in eine der beiden Hälften (oder gibt direkt zurück, falls Pivot bereits an der gesuchten Position liegt). Das macht den Unterschied zwischen \(O(n \log n)\) und \(O(n)\) erwartet.

Bei einem Aufruf von QuickSelect ist die Anzahl Vergleiche \(T = \sum_{i=1}^{N} (r_i - \ell_i)\), wobei \(N\) die Anzahl Partition-Aufrufe ist.
Field-by-field Comparison
Field Before After
Text <b>Selektionsproblem:</b> Bestimme in einer Folge \((A[1], \ldots, A[n])\) paarweise verschiedener Zahlen den {{c1::\(k\)-kleinsten Wert}}.<br><br>Naiver Ansatz: Sortieren + Index, Laufzeit \(O({{c2::n \log n}})\).<br><br>Schneller geht es mit <b>QuickSelect</b> (erwartet \(O({{c3::n}})\)):<pre>QuickSelect(A, ℓ, r, k): p ← Uniform({ℓ, ℓ+1, ..., r}) t ← Partition(A, ℓ, r, p) if t = ℓ + k - 1: return A[t] # gefunden else if t &gt; ℓ + k - 1: return QuickSelect(A, ℓ, t-1, k) # links else: return QuickSelect(A, t+1, r, k - t) # rechts</pre> <b>Selektionsproblem:</b> Bestimme in einer Folge \((A[1], \ldots, A[n])\) paarweise verschiedener Zahlen den {{c1::\(k\)-kleinsten Wert}}.<br><br>Naiver Ansatz: Sortieren + Index, Laufzeit \(O({{c2::n \log n}})\).<br><br>Schneller geht es mit <b>QuickSelect</b> (erwartet \(O({{c3::n}})\)):<br><br><img src="paste-ec2c4055d88b8fe7537faa99452da2cecee1c287.jpg">
Tags: ETH::2._Semester::A&W::2._Wahrscheinlichkeitstheorie_und_randomisierte_Algorithmen::8._Randomisierte_Algorithmen::2._Sortieren_und_Selektieren

Note 2: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: 26IKsH?Yj7
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Bessere Approximation (Faktor \(1\pm\varepsilon\))
Mit {{c1::\(\ell = \lceil \tfrac{100}{\varepsilon^2}\log(2n/\delta)\rceil\)}} Läufen und Rückgabe \(\tilde n_v = -1/\log_2(1-x_v)\) statt \(1/x_v\) erhält man\[(1-\varepsilon)n_v \leq \tilde n_v \leq (1+\varepsilon)n_v\]mit Wahrscheinlichkeit \(\geq 1-\delta\) (ohne Beweis).
Laufzeit: \(O\!\left((n\log n + m)\log(n/\delta)/\varepsilon^2\right)\).

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Bessere Approximation (Faktor \(1\pm\varepsilon\))
Mit {{c1::\(\ell = \lceil \tfrac{100}{\varepsilon^2}\log(2n/\delta)\rceil\)}} Läufen und Rückgabe \(\tilde n_v = -1/\log_2(1-x_v)\) statt \(1/x_v\) erhält man\[(1-\varepsilon)n_v \leq \tilde n_v \leq (1+\varepsilon)n_v\]mit Wahrscheinlichkeit \(\geq 1-\delta\) (ohne Beweis).
Laufzeit: \(O\!\left((n\log n + m)\log(n/\delta)/\varepsilon^2\right)\).

Hintergrund: \(-1/\log_2(1-x) = \ln(2)/x \pm O(1)\). Der Faktor \(1/\varepsilon^2\) ist typisch für solche Konzentrations-Argumente.
Field-by-field Comparison
Field Before After
Text <b>Bessere Approximation (Faktor \(1\pm\varepsilon\))</b><br>Mit {{c1::\(\ell = \lceil \tfrac{100}{\varepsilon^2}\log(2n/\delta)\rceil\)}} Läufen und Rückgabe {{c2::\(\tilde n_v = -1/\log_2(1-x_v)\)}} statt \(1/x_v\) erhält man\[(1-\varepsilon)n_v \leq \tilde n_v \leq (1+\varepsilon)n_v\]mit Wahrscheinlichkeit \(\geq 1-\delta\) (ohne Beweis).<br>Laufzeit: {{c3::\(O\!\left((n\log n + m)\log(n/\delta)/\varepsilon^2\right)\)}}.
Extra Hintergrund: \(-1/\log_2(1-x) = \ln(2)/x \pm O(1)\). Der Faktor \(1/\varepsilon^2\) ist typisch für solche Konzentrations-Argumente.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 3: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: >+74jnc/
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Analyse Teil 2: Schranke für \(\tilde n_v \geq 20 n_v\)
Definiere \(Y'_{i,v}=1\) falls \(x_{i,v} \leq \tfrac{1}{20 n_v}\), sonst \(0\). Mit dem Union-Bound-Fakt \(1-(1-x)^n \leq nx\):\[\Pr[Y'_{i,v}=1] = 1-\left(1-\tfrac{1}{20n_v}\right)^{n_v} \leq {{c1::\tfrac{1}{20} }}\]Aus \(\tilde n_v \geq 20 n_v\) folgt \(\sum_i Y'_{i,v} \geq \ell/2\), also mit Chernoff\[\Pr[\tilde n_v \geq 20 n_v] \leq {{c2::2^{-\ell/2} \leq \tfrac{\delta}{2n} }}\]

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Analyse Teil 2: Schranke für \(\tilde n_v \geq 20 n_v\)
Definiere \(Y'_{i,v}=1\) falls \(x_{i,v} \leq \tfrac{1}{20 n_v}\), sonst \(0\). Mit dem Union-Bound-Fakt \(1-(1-x)^n \leq nx\):\[\Pr[Y'_{i,v}=1] = 1-\left(1-\tfrac{1}{20n_v}\right)^{n_v} \leq {{c1::\tfrac{1}{20} }}\]Aus \(\tilde n_v \geq 20 n_v\) folgt \(\sum_i Y'_{i,v} \geq \ell/2\), also mit Chernoff\[\Pr[\tilde n_v \geq 20 n_v] \leq {{c2::2^{-\ell/2} \leq \tfrac{\delta}{2n} }}\]
Field-by-field Comparison
Field Before After
Text <b>Analyse Teil 2: Schranke für \(\tilde n_v \geq 20 n_v\)</b><br>Definiere \(Y'_{i,v}=1\) falls \(x_{i,v} \leq \tfrac{1}{20 n_v}\), sonst \(0\). Mit dem Union-Bound-Fakt \(1-(1-x)^n \leq nx\):\[\Pr[Y'_{i,v}=1] = 1-\left(1-\tfrac{1}{20n_v}\right)^{n_v} \leq {{c1::\tfrac{1}{20} }}\]Aus \(\tilde n_v \geq 20 n_v\) folgt \(\sum_i Y'_{i,v} \geq \ell/2\), also mit Chernoff\[\Pr[\tilde n_v \geq 20 n_v] \leq {{c2::2^{-\ell/2} \leq \tfrac{\delta}{2n} }}\]
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 4: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: >I4:X:)egN
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
ReachabilityCounting: finaler Union Bound
Je Knoten \(v\) gilt \(\Pr[\tilde n_v \leq n_v/20] \leq \tfrac{\delta}{2n}\) und \(\Pr[\tilde n_v \geq 20 n_v] \leq \tfrac{\delta}{2n}\).
Über alle \(n\) Knoten und beide Seiten liefert der Union Bound eine Fehlerwahrscheinlichkeit \(\leq {{c1::2n \cdot \tfrac{\delta}{2n} = \delta}}\), also Erfolg mit Wahrscheinlichkeit \(\geq 1-\delta\).

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
ReachabilityCounting: finaler Union Bound
Je Knoten \(v\) gilt \(\Pr[\tilde n_v \leq n_v/20] \leq \tfrac{\delta}{2n}\) und \(\Pr[\tilde n_v \geq 20 n_v] \leq \tfrac{\delta}{2n}\).
Über alle \(n\) Knoten und beide Seiten liefert der Union Bound eine Fehlerwahrscheinlichkeit \(\leq {{c1::2n \cdot \tfrac{\delta}{2n} = \delta}}\), also Erfolg mit Wahrscheinlichkeit \(\geq 1-\delta\).
Field-by-field Comparison
Field Before After
Text <b>ReachabilityCounting: finaler Union Bound</b><br>Je Knoten \(v\) gilt \(\Pr[\tilde n_v \leq n_v/20] \leq \tfrac{\delta}{2n}\) und \(\Pr[\tilde n_v \geq 20 n_v] \leq \tfrac{\delta}{2n}\).<br>Über alle \(n\) Knoten und beide Seiten liefert der Union Bound eine Fehlerwahrscheinlichkeit \(\leq {{c1::2n \cdot \tfrac{\delta}{2n} = \delta}}\), also Erfolg mit Wahrscheinlichkeit \(\geq {{c2::1-\delta}}\).
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 5: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: G=p3gO|{IJ
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Randkante.
Ein Paar \(qr \in P^2\), \(q \neq r\), heisst Randkante von \(P\), falls {{c1::alle Punkte in \(P \setminus \{q, r\}\) links von \(q, r\) liegen}} (d.h. auf der linken Seite der von \(q\) nach \(r\) gerichteten Geraden).

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Randkante.
Ein Paar \(qr \in P^2\), \(q \neq r\), heisst Randkante von \(P\), falls {{c1::alle Punkte in \(P \setminus \{q, r\}\) links von \(q, r\) liegen}} (d.h. auf der linken Seite der von \(q\) nach \(r\) gerichteten Geraden).

Diese gerichtete Sichtweise legt direkt die Gegen-Uhrzeigersinn-Orientierung der Hülle fest.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Randkante.
Ein Paar \(qr \in P^2\), \(q \neq r\), heisst Randkante von \(P\), falls {{c1::alle Punkte in \(P \setminus \{q, r\}\) links von \(q, r\) liegen (d.h. auf der linken Seite der von \(q\) nach \(r\) gerichteten Geraden)}}.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Randkante.
Ein Paar \(qr \in P^2\), \(q \neq r\), heisst Randkante von \(P\), falls {{c1::alle Punkte in \(P \setminus \{q, r\}\) links von \(q, r\) liegen (d.h. auf der linken Seite der von \(q\) nach \(r\) gerichteten Geraden)}}.



Diese gerichtete Sichtweise legt direkt die Gegen-Uhrzeigersinn-Orientierung der Hülle fest.
Field-by-field Comparison
Field Before After
Text <b>Randkante.</b><br>Ein Paar \(qr \in P^2\), \(q \neq r\), heisst <b>Randkante</b> von \(P\), falls {{c1::alle Punkte in \(P \setminus \{q, r\}\) links von \(q, r\) liegen}} (d.h. auf der linken Seite der von \(q\) nach \(r\) gerichteten Geraden). <b>Randkante.</b><br>Ein Paar \(qr \in P^2\), \(q \neq r\), heisst <b>Randkante</b> von \(P\), falls {{c1::alle Punkte in \(P \setminus \{q, r\}\) links von \(q, r\) liegen (d.h. auf der linken Seite der von \(q\) nach \(r\) gerichteten Geraden)}}.
Extra Diese gerichtete Sichtweise legt direkt die Gegen-Uhrzeigersinn-Orientierung der Hülle fest. <img src="paste-b9d6d6da2e7f4e631030fd61a74aff893741ae56.jpg"><br><br>Diese gerichtete Sichtweise legt direkt die Gegen-Uhrzeigersinn-Orientierung der Hülle fest.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 6: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: J~>ftA6Yjk
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Idee hinter der Erreichbarkeits-Approximation
Wähle \(r_v \leftarrow \mathrm{Uniform}([0,1])\) und setze \(x_v = \min_{u \in R(v)} r_u\).

Dann ist \(x_v\) das Minimum von \(n_v\) Zufallszahlen in \([0,1]\), also grob \(x_v \approx 1/n_v\).
Folglich ist \(1/x_v\) eine Schätzung für \(n_v\).
Den Fehler reduziert man, indem man über mehrere Läufe den Median bildet.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Idee hinter der Erreichbarkeits-Approximation
Wähle \(r_v \leftarrow \mathrm{Uniform}([0,1])\) und setze \(x_v = \min_{u \in R(v)} r_u\).

Dann ist \(x_v\) das Minimum von \(n_v\) Zufallszahlen in \([0,1]\), also grob \(x_v \approx 1/n_v\).
Folglich ist \(1/x_v\) eine Schätzung für \(n_v\).
Den Fehler reduziert man, indem man über mehrere Läufe den Median bildet.
Field-by-field Comparison
Field Before After
Text <b>Idee hinter der Erreichbarkeits-Approximation</b><br>Wähle \(r_v \leftarrow \mathrm{Uniform}([0,1])\) und setze \(x_v = \min_{u \in R(v)} r_u\).<br><br>Dann ist \(x_v\) das {{c1::Minimum von \(n_v\) Zufallszahlen in \([0,1]\)}}, also grob \(x_v \approx {{c2::1/n_v}}\).<br>Folglich ist {{c3::\(1/x_v\)}} eine Schätzung für \(n_v\).<br>Den Fehler reduziert man, indem man über mehrere Läufe den {{c4::Median}} bildet.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 7: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: Ong0`FNR)`
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Darstellung der konvexen Hülle (endliches \(P\) in der Ebene).
Der Rand von \(\operatorname{conv}(P)\) ist ein Polygon, dessen Ecken Punkte aus \(P\) sind. Die Berechnung von \(\operatorname{conv}(P)\) meint die Bestimmung der Eckenfolge \((q_0, q_1, \ldots, q_{h-1})\), \(h \leq n\), beginnend bei beliebigem \(q_0\) und gegen den Uhrzeigersinn entlang des Polygons.

Dabei ist \(Q := \{q_0, \ldots, q_{h-1}\}\) {{c4::die kleinste Teilmenge von \(P\) mit \(\operatorname{conv}(Q) = \operatorname{conv}(P)\)}}.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Darstellung der konvexen Hülle (endliches \(P\) in der Ebene).
Der Rand von \(\operatorname{conv}(P)\) ist ein Polygon, dessen Ecken Punkte aus \(P\) sind. Die Berechnung von \(\operatorname{conv}(P)\) meint die Bestimmung der Eckenfolge \((q_0, q_1, \ldots, q_{h-1})\), \(h \leq n\), beginnend bei beliebigem \(q_0\) und gegen den Uhrzeigersinn entlang des Polygons.

Dabei ist \(Q := \{q_0, \ldots, q_{h-1}\}\) {{c4::die kleinste Teilmenge von \(P\) mit \(\operatorname{conv}(Q) = \operatorname{conv}(P)\)}}.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Darstellung der konvexen Hülle (endliches \(P\) in der Ebene).

Der Rand von \(\operatorname{conv}(P)\) ist ein Polygon, dessen Ecken Punkte aus \(P\) sind.

Die Berechnung von \(\operatorname{conv}(P)\) meint {{c2::die Bestimmung der Eckenfolge \((q_0, q_1, \ldots, q_{h-1})\), \(h \leq n\), beginnend bei beliebigem \(q_0\) und gegen den Uhrzeigersinn entlang des Polygons}}.

Dabei ist \(Q := \{q_0, \ldots, q_{h-1}\}\) {{c3::die kleinste Teilmenge von \(P\) mit \(\operatorname{conv}(Q) = \operatorname{conv}(P)\)}}.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Darstellung der konvexen Hülle (endliches \(P\) in der Ebene).

Der Rand von \(\operatorname{conv}(P)\) ist ein Polygon, dessen Ecken Punkte aus \(P\) sind.

Die Berechnung von \(\operatorname{conv}(P)\) meint {{c2::die Bestimmung der Eckenfolge \((q_0, q_1, \ldots, q_{h-1})\), \(h \leq n\), beginnend bei beliebigem \(q_0\) und gegen den Uhrzeigersinn entlang des Polygons}}.

Dabei ist \(Q := \{q_0, \ldots, q_{h-1}\}\) {{c3::die kleinste Teilmenge von \(P\) mit \(\operatorname{conv}(Q) = \operatorname{conv}(P)\)}}.

Field-by-field Comparison
Field Before After
Text <b>Darstellung der konvexen Hülle (endliches \(P\) in der Ebene).</b><br>Der Rand von \(\operatorname{conv}(P)\) ist ein {{c1::Polygon}}, dessen Ecken {{c2::Punkte aus \(P\)}} sind. Die Berechnung von \(\operatorname{conv}(P)\) meint die Bestimmung der Eckenfolge \((q_0, q_1, \ldots, q_{h-1})\), \(h \leq n\), beginnend bei beliebigem \(q_0\) und {{c3::gegen den Uhrzeigersinn}} entlang des Polygons.<br><br>Dabei ist \(Q := \{q_0, \ldots, q_{h-1}\}\) {{c4::die kleinste Teilmenge von \(P\) mit \(\operatorname{conv}(Q) = \operatorname{conv}(P)\)}}. <b>Darstellung der konvexen Hülle (endliches \(P\) in der Ebene).<br></b><br>Der Rand von \(\operatorname{conv}(P)\) ist {{c1::ein Polygon, dessen Ecken Punkte aus \(P\)&nbsp;sind}}. <br><br>Die Berechnung von \(\operatorname{conv}(P)\) meint {{c2::die Bestimmung der Eckenfolge \((q_0, q_1, \ldots, q_{h-1})\), \(h \leq n\), beginnend bei beliebigem \(q_0\) und gegen den Uhrzeigersinn entlang des Polygons}}.<br><br>Dabei ist \(Q := \{q_0, \ldots, q_{h-1}\}\) {{c3::die kleinste Teilmenge von \(P\) mit \(\operatorname{conv}(Q) = \operatorname{conv}(P)\)}}.
Extra <img src="paste-ac70a22dd833024a4b1adf4e88511aa32750c621.jpg">
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 8: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: Q.ArG%jeIn
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Union-Bound-Fakt
Für alle \(x \in [0,1]\) und \(n \in \mathbb{N}\) gilt\[1 - (1-x)^n \leq n x\]Beweisidee: Für unabhängige \(X_1,\ldots,X_n \sim \mathrm{Ber}(x)\) ist \(\Pr[X_1=1 \vee \ldots \vee X_n=1] = 1-(1-x)^n\); die Union Bound liefert andererseits \(\Pr[X_1=1 \vee \ldots \vee X_n=1] \leq \sum_i \Pr[X_i=1] = n x\).

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Union-Bound-Fakt
Für alle \(x \in [0,1]\) und \(n \in \mathbb{N}\) gilt\[1 - (1-x)^n \leq n x\]Beweisidee: Für unabhängige \(X_1,\ldots,X_n \sim \mathrm{Ber}(x)\) ist \(\Pr[X_1=1 \vee \ldots \vee X_n=1] = 1-(1-x)^n\); die Union Bound liefert andererseits \(\Pr[X_1=1 \vee \ldots \vee X_n=1] \leq \sum_i \Pr[X_i=1] = n x\).

Spezialfall der Booleschen Ungleichung, im Beweis von ReachabilityCounting (Teil 2) verwendet.
Field-by-field Comparison
Field Before After
Text <b>Union-Bound-Fakt</b><br>Für alle \(x \in [0,1]\) und \(n \in \mathbb{N}\) gilt\[{{c1::1 - (1-x)^n \leq n x}}\]Beweisidee: Für unabhängige \(X_1,\ldots,X_n \sim \mathrm{Ber}(x)\) ist \(\Pr[X_1=1 \vee \ldots \vee X_n=1] = {{c2::1-(1-x)^n}}\); die Union Bound liefert andererseits \(\Pr[X_1=1 \vee \ldots \vee X_n=1] \leq \sum_i \Pr[X_i=1] = {{c3::n x}}\).
Extra Spezialfall der Booleschen Ungleichung, im Beweis von ReachabilityCounting (Teil 2) verwendet.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 9: ETH::2. Semester::A&W

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Nützliche Subroutine
Gegeben ein gerichteter Graph \(G\) und Zahlen \(r_v\), berechne für jeden Knoten \(v\) die kleinste erreichbare Zahl \(\min_{u \in R(v)} r_u\).

Naiv \(O(n(n+m))\). Verbesserung auf \(O(n \log n + m)\):
Sortiere die Knoten aufsteigend nach \(r_v\) und starte von jedem noch unbesuchten Knoten eine Rückwärts-DFS (entlang eingehender Kanten), die \(\min[\cdot]\) auf den aktuellen Wert setzt.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Nützliche Subroutine
Gegeben ein gerichteter Graph \(G\) und Zahlen \(r_v\), berechne für jeden Knoten \(v\) die kleinste erreichbare Zahl \(\min_{u \in R(v)} r_u\).

Naiv \(O(n(n+m))\). Verbesserung auf \(O(n \log n + m)\):
Sortiere die Knoten aufsteigend nach \(r_v\) und starte von jedem noch unbesuchten Knoten eine Rückwärts-DFS (entlang eingehender Kanten), die \(\min[\cdot]\) auf den aktuellen Wert setzt.

Subroutine(G, r):
  sortiere V aufsteigend nach r_v: v_1, ..., v_n
  min[v] := ∞ für alle v
  for i = 1, ..., n:
    if min[v_i] = ∞:
      DFSrev(v_i, r_{v_i})
  return min

DFSrev(v, r):
  min[v] := r
  for each eingehender Nachbar u von v:
    if min[u] = ∞:
      DFSrev(u, r)
Bemerkung: Hier ist \(\min\) einfacher zu berechnen als eine Summe \(\sum\).
Field-by-field Comparison
Field Before After
Text <b>Nützliche Subroutine</b><br>Gegeben ein gerichteter Graph \(G\) und Zahlen \(r_v\), berechne für jeden Knoten \(v\) die kleinste erreichbare Zahl \(\min_{u \in R(v)} r_u\).<br><br>Naiv \(O(n(n+m))\). Verbesserung auf {{c1::\(O(n \log n + m)\)}}:<br>Sortiere die Knoten {{c2::aufsteigend nach \(r_v\)}} und starte von jedem noch unbesuchten Knoten eine {{c3::Rückwärts-DFS (entlang eingehender Kanten)}}, die \(\min[\cdot]\) auf den aktuellen Wert setzt.
Extra <pre>Subroutine(G, r): sortiere V aufsteigend nach r_v: v_1, ..., v_n min[v] := ∞ für alle v for i = 1, ..., n: if min[v_i] = ∞: DFSrev(v_i, r_{v_i}) return min DFSrev(v, r): min[v] := r for each eingehender Nachbar u von v: if min[u] = ∞: DFSrev(u, r)</pre>Bemerkung: Hier ist \(\min\) einfacher zu berechnen als eine Summe \(\sum\).
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 10: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: SLT}g*q+Wj
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Anmerkungen zu LocalRepair.
  • Degeneriertheiten sind einfach einzubeziehen (lexikographisch sortieren, Duplikate danach entfernen, Test adaptieren).
  • Numerisch robuster als JarvisWrap: kann nie in eine unendliche Schleife laufen.
  • Liefert nebenbei eine Triangulierung der Punkte (lokale Verbesserung dient auch zur Berechnung guter, etwa Delaunay-, Triangulierungen).
  • Optimal, aber: es gibt auch einen \(O(n \log h)\)-Algorithmus; für Punkte zufällig aus Quadrat/Kreisscheibe sogar erwartet \(O(n)\).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Anmerkungen zu LocalRepair.
  • Degeneriertheiten sind einfach einzubeziehen (lexikographisch sortieren, Duplikate danach entfernen, Test adaptieren).
  • Numerisch robuster als JarvisWrap: kann nie in eine unendliche Schleife laufen.
  • Liefert nebenbei eine Triangulierung der Punkte (lokale Verbesserung dient auch zur Berechnung guter, etwa Delaunay-, Triangulierungen).
  • Optimal, aber: es gibt auch einen \(O(n \log h)\)-Algorithmus; für Punkte zufällig aus Quadrat/Kreisscheibe sogar erwartet \(O(n)\).

After

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Anmerkungen zu LocalRepair.
  • Degeneriertheiten sind einfach einzubeziehen (lexikographisch sortieren, Duplikate danach entfernen, Test adaptieren).
  • Numerisch robuster als JarvisWrap: kann nie in eine unendliche Schleife laufen.
  • Liefert nebenbei eine Triangulierung der Punkte (lokale Verbesserung dient auch zur Berechnung guter, etwa Delaunay-, Triangulierungen).
  • Optimal, aber: es gibt auch einen \(O(n \log h)\)-Algorithmus; für Punkte zufällig aus Quadrat/Kreisscheibe sogar erwartet \(O(n)\).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Anmerkungen zu LocalRepair.
  • Degeneriertheiten sind einfach einzubeziehen (lexikographisch sortieren, Duplikate danach entfernen, Test adaptieren).
  • Numerisch robuster als JarvisWrap: kann nie in eine unendliche Schleife laufen.
  • Liefert nebenbei eine Triangulierung der Punkte (lokale Verbesserung dient auch zur Berechnung guter, etwa Delaunay-, Triangulierungen).
  • Optimal, aber: es gibt auch einen \(O(n \log h)\)-Algorithmus; für Punkte zufällig aus Quadrat/Kreisscheibe sogar erwartet \(O(n)\).
Field-by-field Comparison
Field Before After
Text <b>Anmerkungen zu LocalRepair.</b><br><ul><li>Degeneriertheiten sind einfach einzubeziehen (lexikographisch sortieren, Duplikate danach entfernen, Test adaptieren).</li><li>Numerisch {{c1::robuster als JarvisWrap}}: kann nie in eine unendliche Schleife laufen.</li><li>Liefert nebenbei {{c2::eine Triangulierung der Punkte}} (lokale Verbesserung dient auch zur Berechnung guter, etwa Delaunay-, Triangulierungen).</li><li>Optimal, aber: es gibt auch einen {{c3::\(O(n \log h)\)}}-Algorithmus; für Punkte zufällig aus Quadrat/Kreisscheibe sogar erwartet {{c4::\(O(n)\)}}.</li></ul> <b>Anmerkungen zu LocalRepair.</b><br><ul><li>Degeneriertheiten sind einfach einzubeziehen (lexikographisch sortieren, Duplikate danach entfernen, Test adaptieren).</li><li>Numerisch {{c1::robuster als JarvisWrap: kann nie in eine unendliche Schleife laufen}}.</li><li>Liefert nebenbei {{c2::eine Triangulierung der Punkte (lokale Verbesserung dient auch zur Berechnung guter, etwa Delaunay-, Triangulierungen)}}.</li><li>Optimal, aber: es gibt auch einen {{c3::\(O(n \log h)\)}}-Algorithmus; für Punkte zufällig aus Quadrat/Kreisscheibe sogar erwartet {{c3::\(O(n)\)}}.</li></ul>
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 11: ETH::2. Semester::A&W

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Approximation der Erreichbarkeit (gerichtet)
Die Menge der von \(v\) erreichbaren Knoten ist \(R(v) = \{u \in V : u \text{ von } v \text{ erreichbar}\}\), und man schreibt \(n_v = |R(v)|\) für ihre Grösse.

Da exaktes Zählen vermutlich nicht nahe-linear geht, approximiert man \(n_v\): berechne \(\tilde n_v\) mit {{c2::\(\tfrac{n_v}{20} \leq \tilde n_v \leq 20 n_v\)}} (oder sogar \((1-\varepsilon)n_v \leq \tilde n_v \leq (1+\varepsilon)n_v\)).

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Approximation der Erreichbarkeit (gerichtet)
Die Menge der von \(v\) erreichbaren Knoten ist \(R(v) = \{u \in V : u \text{ von } v \text{ erreichbar}\}\), und man schreibt \(n_v = |R(v)|\) für ihre Grösse.

Da exaktes Zählen vermutlich nicht nahe-linear geht, approximiert man \(n_v\): berechne \(\tilde n_v\) mit {{c2::\(\tfrac{n_v}{20} \leq \tilde n_v \leq 20 n_v\)}} (oder sogar \((1-\varepsilon)n_v \leq \tilde n_v \leq (1+\varepsilon)n_v\)).
Field-by-field Comparison
Field Before After
Text <b>Approximation der Erreichbarkeit (gerichtet)</b><br>Die Menge der von \(v\) erreichbaren Knoten ist \(R(v) = \{u \in V : u \text{ von } v \text{ erreichbar}\}\), und man schreibt {{c1::\(n_v = |R(v)|\)}} für ihre Grösse.<br><br>Da exaktes Zählen vermutlich nicht nahe-linear geht, approximiert man \(n_v\): berechne \(\tilde n_v\) mit {{c2::\(\tfrac{n_v}{20} \leq \tilde n_v \leq 20 n_v\)}} (oder sogar \((1-\varepsilon)n_v \leq \tilde n_v \leq (1+\varepsilon)n_v\)).
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 12: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Vereinfachende Annahme: Allgemeine Lage.
Für die ConvexHull-Algorithmen nimmt man an, dass keine 3 Punkte auf einer gemeinsamen Geraden liegen und keine 2 Punkte dieselbe \(x\)-Koordinate haben.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Vereinfachende Annahme: Allgemeine Lage.
Für die ConvexHull-Algorithmen nimmt man an, dass keine 3 Punkte auf einer gemeinsamen Geraden liegen und keine 2 Punkte dieselbe \(x\)-Koordinate haben.

Diese Annahme schliesst Kollinearitäten und Mehrdeutigkeiten aus: Degeneriertheiten werden separat behandelt.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Vereinfachende Annahme: Allgemeine Lage.
Für die ConvexHull-Algorithmen nimmt man an, dass keine 3 Punkte auf einer gemeinsamen Geraden liegen und keine 2 Punkte dieselbe \(x\)-Koordinate haben.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Vereinfachende Annahme: Allgemeine Lage.
Für die ConvexHull-Algorithmen nimmt man an, dass keine 3 Punkte auf einer gemeinsamen Geraden liegen und keine 2 Punkte dieselbe \(x\)-Koordinate haben.

Diese Annahme schliesst Kollinearitäten und Mehrdeutigkeiten aus: Degeneriertheiten werden separat behandelt.
Field-by-field Comparison
Field Before After
Text <b>Vereinfachende Annahme: Allgemeine Lage.</b><br>Für die ConvexHull-Algorithmen nimmt man an, dass {{c1::keine 3 Punkte auf einer gemeinsamen Geraden liegen}} und {{c2::keine 2 Punkte dieselbe \(x\)-Koordinate haben}}. <b>Vereinfachende Annahme: Allgemeine Lage.</b><br>Für die ConvexHull-Algorithmen nimmt man an, dass {{c1::keine 3 Punkte auf einer gemeinsamen Geraden liegen}} und {{c1::keine 2 Punkte dieselbe \(x\)-Koordinate haben}}.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 13: ETH::2. Semester::A&W

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
ReachabilityCounting (Faktor-20-Approximation)
Wähle \(\ell = \lceil 2 \log_2(2n/\delta) \rceil\) Läufe. In jedem Lauf \(i\): ziehe \(r_{i,v} \sim \mathrm{Uniform}([0,1])\) und berechne \(x_{i,v} = \min_{u\in R(v)} r_{i,u}\) mit der Subroutine.
Setze \(x_v = \mathrm{Median}(x_{1,v}, \ldots, x_{\ell,v})\) und gib \(\tilde n_v = 1/x_v\) zurück.

Laufzeit: \(O((n \log n + m)\log(n/\delta))\).

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
ReachabilityCounting (Faktor-20-Approximation)
Wähle \(\ell = \lceil 2 \log_2(2n/\delta) \rceil\) Läufe. In jedem Lauf \(i\): ziehe \(r_{i,v} \sim \mathrm{Uniform}([0,1])\) und berechne \(x_{i,v} = \min_{u\in R(v)} r_{i,u}\) mit der Subroutine.
Setze \(x_v = \mathrm{Median}(x_{1,v}, \ldots, x_{\ell,v})\) und gib \(\tilde n_v = 1/x_v\) zurück.

Laufzeit: \(O((n \log n + m)\log(n/\delta))\).

ReachabilityCounting(G):
  ℓ := ⌈2 log_2(2n/δ)⌉
  for i = 1, ..., ℓ:
    r_{i,v} := Uniform([0,1]) für alle v
    x_{i,v} := min_{u ∈ R(v)} r_{i,u}   # Subroutine, O(n log n + m)
  x_v := Median(x_{1,v}, ..., x_{ℓ,v}) für alle v
  return ñ_v := 1/x_v für alle v
Field-by-field Comparison
Field Before After
Text <b>ReachabilityCounting (Faktor-20-Approximation)</b><br>Wähle {{c1::\(\ell = \lceil 2 \log_2(2n/\delta) \rceil\)}} Läufe. In jedem Lauf \(i\): ziehe \(r_{i,v} \sim \mathrm{Uniform}([0,1])\) und berechne \(x_{i,v} = \min_{u\in R(v)} r_{i,u}\) mit der Subroutine.<br>Setze \(x_v = \mathrm{Median}(x_{1,v}, \ldots, x_{\ell,v})\) und gib {{c2::\(\tilde n_v = 1/x_v\)}} zurück.<br><br>Laufzeit: {{c3::\(O((n \log n + m)\log(n/\delta))\)}}.
Extra <pre>ReachabilityCounting(G): ℓ := ⌈2 log_2(2n/δ)⌉ for i = 1, ..., ℓ: r_{i,v} := Uniform([0,1]) für alle v x_{i,v} := min_{u ∈ R(v)} r_{i,u} # Subroutine, O(n log n + m) x_v := Median(x_{1,v}, ..., x_{ℓ,v}) für alle v return ñ_v := 1/x_v für alle v</pre>
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 14: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: XGaR5ZRd8Z
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Konsequenz der Invarianten + Nichtdeterminismus.
Dank der drei Invarianten gilt: lokal konvex \(\Rightarrow\) Lösungspolygon (kein Selbstschnitt, alle Punkte umschlossen).

Ausserdem ist der Algorithmus zunächst nicht-deterministisch: die lokalen Verbesserungsschritte dürfen in beliebiger Reihenfolge ausgeführt werden.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Konsequenz der Invarianten + Nichtdeterminismus.
Dank der drei Invarianten gilt: lokal konvex \(\Rightarrow\) Lösungspolygon (kein Selbstschnitt, alle Punkte umschlossen).

Ausserdem ist der Algorithmus zunächst nicht-deterministisch: die lokalen Verbesserungsschritte dürfen in beliebiger Reihenfolge ausgeführt werden.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Konsequenz der Invarianten + Nichtdeterminismus.
Dank der drei Invarianten gilt: lokal konvex \(\Rightarrow\) Lösungspolygon (kein Selbstschnitt, alle Punkte umschlossen).

Ausserdem ist der Algorithmus zunächst nicht-deterministisch: die lokalen Verbesserungsschritte dürfen in beliebiger Reihenfolge ausgeführt werden.

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Konsequenz der Invarianten + Nichtdeterminismus.
Dank der drei Invarianten gilt: lokal konvex \(\Rightarrow\) Lösungspolygon (kein Selbstschnitt, alle Punkte umschlossen).

Ausserdem ist der Algorithmus zunächst nicht-deterministisch: die lokalen Verbesserungsschritte dürfen in beliebiger Reihenfolge ausgeführt werden.
Field-by-field Comparison
Field Before After
Text <b>Konsequenz der Invarianten + Nichtdeterminismus.</b><br>Dank der drei Invarianten gilt: {{c1::lokal konvex \(\Rightarrow\) Lösungspolygon}} (kein Selbstschnitt, alle Punkte umschlossen).<br><br>Ausserdem ist der Algorithmus zunächst {{c2::nicht-deterministisch}}: die lokalen Verbesserungsschritte dürfen in {{c2::beliebiger Reihenfolge}} ausgeführt werden. <b>Konsequenz der Invarianten + Nichtdeterminismus.</b><br>Dank der drei Invarianten gilt: {{c1::lokal konvex \(\Rightarrow\) Lösungspolygon (kein Selbstschnitt, alle Punkte umschlossen)}}.<br><br>Ausserdem ist der Algorithmus zunächst {{c2::nicht-deterministisch}}: die lokalen Verbesserungsschritte dürfen in {{c2::beliebiger Reihenfolge}} ausgeführt werden.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 15: ETH::2. Semester::A&W

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Analyse Teil 1: Schranke für \(\tilde n_v \leq n_v/20\)
Definiere \(Y_{i,v} = 1\) falls \(x_{i,v} \geq 20/n_v\), sonst \(0\). Da \(x_{i,v}\) das Minimum von \(n_v\) Uniformen ist:\[\Pr[Y_{i,v}=1] = {{c1::\left(1 - \tfrac{20}{n_v}\right)^{n_v} \leq e^{-20} }}\]Aus \(\tilde n_v \leq n_v/20\) folgt \(x_v \geq 20/n_v\), also \(x_{i,v}\geq 20/n_v\) für mindestens \(\ell/2\) der \(i\), d.h. \(\sum_i Y_{i,v} \geq \ell/2\).
Mit der Chernoff-Schranke \(\Pr[X\geq t]\leq 2^{-t}\) für \(t \geq 2e\,\mathbb{E}[X]\):\[\Pr\!\left[\tilde n_v \leq \tfrac{n_v}{20}\right] \leq {{c3::2^{-\ell/2} \leq \tfrac{\delta}{2n} }}\]

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Analyse Teil 1: Schranke für \(\tilde n_v \leq n_v/20\)
Definiere \(Y_{i,v} = 1\) falls \(x_{i,v} \geq 20/n_v\), sonst \(0\). Da \(x_{i,v}\) das Minimum von \(n_v\) Uniformen ist:\[\Pr[Y_{i,v}=1] = {{c1::\left(1 - \tfrac{20}{n_v}\right)^{n_v} \leq e^{-20} }}\]Aus \(\tilde n_v \leq n_v/20\) folgt \(x_v \geq 20/n_v\), also \(x_{i,v}\geq 20/n_v\) für mindestens \(\ell/2\) der \(i\), d.h. \(\sum_i Y_{i,v} \geq \ell/2\).
Mit der Chernoff-Schranke \(\Pr[X\geq t]\leq 2^{-t}\) für \(t \geq 2e\,\mathbb{E}[X]\):\[\Pr\!\left[\tilde n_v \leq \tfrac{n_v}{20}\right] \leq {{c3::2^{-\ell/2} \leq \tfrac{\delta}{2n} }}\]

Es gilt \(\mathbb{E}\!\left[\sum_i Y_{i,v}\right] \leq \ell\, e^{-20} \leq \tfrac{\ell}{2\cdot 2e}\), weshalb die Chernoff-Voraussetzung \(t = \ell/2 \geq 2e\,\mathbb{E}[\sum_i Y_{i,v}]\) erfüllt ist.
Field-by-field Comparison
Field Before After
Text <b>Analyse Teil 1: Schranke für \(\tilde n_v \leq n_v/20\)</b><br>Definiere \(Y_{i,v} = 1\) falls \(x_{i,v} \geq 20/n_v\), sonst \(0\). Da \(x_{i,v}\) das Minimum von \(n_v\) Uniformen ist:\[\Pr[Y_{i,v}=1] = {{c1::\left(1 - \tfrac{20}{n_v}\right)^{n_v} \leq e^{-20} }}\]Aus \(\tilde n_v \leq n_v/20\) folgt \(x_v \geq 20/n_v\), also \(x_{i,v}\geq 20/n_v\) für mindestens {{c2::\(\ell/2\)}} der \(i\), d.h. \(\sum_i Y_{i,v} \geq \ell/2\).<br>Mit der Chernoff-Schranke \(\Pr[X\geq t]\leq 2^{-t}\) für \(t \geq 2e\,\mathbb{E}[X]\):\[\Pr\!\left[\tilde n_v \leq \tfrac{n_v}{20}\right] \leq {{c3::2^{-\ell/2} \leq \tfrac{\delta}{2n} }}\]
Extra Es gilt \(\mathbb{E}\!\left[\sum_i Y_{i,v}\right] \leq \ell\, e^{-20} \leq \tfrac{\ell}{2\cdot 2e}\), weshalb die Chernoff-Voraussetzung \(t = \ell/2 \geq 2e\,\mathbb{E}[\sum_i Y_{i,v}]\) erfüllt ist.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 16: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Classic
GUID: YdaR[CTQLC
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Lemma (Ordnung um eine Hüllen-Ecke).
Sei \(q\) eine Ecke der konvexen Hülle von \(P\). Was gilt für die Relation \(\prec_q\) auf \(P \setminus \{q\}\), und was bedeutet ihr Minimum?

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Lemma (Ordnung um eine Hüllen-Ecke).
Sei \(q\) eine Ecke der konvexen Hülle von \(P\). Was gilt für die Relation \(\prec_q\) auf \(P \setminus \{q\}\), und was bedeutet ihr Minimum?

\(\prec_q\) ist eine totale Ordnung auf \(P \setminus \{q\}\). Für das Minimum \(p_{\min}\) dieser Ordnung gilt: \(q, p_{\min}\) ist eine Randkante.

Damit liefert ein einzelner Min-Durchlauf (wie in FindNext) die nächste Hüllenkante.

After

Front

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Ordnung um eine Hüllen-Ecke.
Sei \(q\) eine Ecke der konvexen Hülle von \(P\). Was gilt für die Relation \(\prec_q\) auf \(P \setminus \{q\}\), und was bedeutet ihr Minimum?

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Ordnung um eine Hüllen-Ecke.
Sei \(q\) eine Ecke der konvexen Hülle von \(P\). Was gilt für die Relation \(\prec_q\) auf \(P \setminus \{q\}\), und was bedeutet ihr Minimum?

\(\prec_q\) ist eine totale Ordnung auf \(P \setminus \{q\}\). Für das Minimum \(p_{\min}\) dieser Ordnung gilt: \(q, p_{\min}\) ist eine Randkante.

Damit liefert ein einzelner Min-Durchlauf (wie in FindNext) die nächste Hüllenkante.

Field-by-field Comparison
Field Before After
Front <b>Lemma (Ordnung um eine Hüllen-Ecke).</b><br>Sei \(q\) eine Ecke der konvexen Hülle von \(P\). Was gilt für die Relation \(\prec_q\) auf \(P \setminus \{q\}\), und was bedeutet ihr Minimum? <b>Ordnung um eine Hüllen-Ecke.</b><br>Sei \(q\) eine Ecke der konvexen Hülle von \(P\). Was gilt für die Relation \(\prec_q\) auf \(P \setminus \{q\}\), und was bedeutet ihr Minimum?
Back \(\prec_q\) ist eine <b>totale Ordnung</b> auf \(P \setminus \{q\}\). Für das Minimum \(p_{\min}\) dieser Ordnung gilt: \(q, p_{\min}\) ist eine <b>Randkante</b>.<br><br>Damit liefert ein einzelner Min-Durchlauf (wie in <code>FindNext</code>) die nächste Hüllenkante. \(\prec_q\) ist eine <b>totale Ordnung</b> auf \(P \setminus \{q\}\). Für das Minimum \(p_{\min}\) dieser Ordnung gilt: \(q, p_{\min}\) ist eine <b>Randkante</b>.<br><br>Damit liefert ein einzelner Min-Durchlauf (wie in <code>FindNext</code>) die nächste Hüllenkante.<br><br><img src="paste-aecdd3cc19feb3435f875933ad9e18b3b9ca0196.jpg">
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 17: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Classic
GUID: ZWq;u<}z8a
added

Previous

Note did not exist

New Note

Front

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Distinct Elements / Count-Distinct
Welches praktische Problem löst dieselbe Idee wie ReachabilityCounting, und wie?

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Distinct Elements / Count-Distinct
Welches praktische Problem löst dieselbe Idee wie ReachabilityCounting, und wie?

Man will die Anzahl unterschiedlicher Nutzer bzw. Aufrufe approximieren, ohne alle Aufrufe zu speichern.

Dieselbe Median-von-Minima-Idee (zufällige Werte ziehen, der kleinste beobachtete Wert schätzt die Anzahl distinkter Elemente) löst das Count-Distinct-Problem. Bekannte Varianten: Flajolet-Martin und HyperLogLog.
Field-by-field Comparison
Field Before After
Front <b>Distinct Elements / Count-Distinct</b><br>Welches praktische Problem löst dieselbe Idee wie ReachabilityCounting, und wie?
Back Man will die Anzahl <b>unterschiedlicher</b> Nutzer bzw. Aufrufe approximieren, ohne alle Aufrufe zu speichern.<br><br>Dieselbe Median-von-Minima-Idee (zufällige Werte ziehen, der kleinste beobachtete Wert schätzt die Anzahl distinkter Elemente) löst das Count-Distinct-Problem. Bekannte Varianten: <b>Flajolet-Martin</b> und <b>HyperLogLog</b>.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 18: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: [,E,9zW4{2
modified

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: numerische Probleme.
Der Orientierungsausdruck \((r_x - q_x)(p_y - q_y) - (p_x - q_x)(r_y - q_y) > 0\) ist mit Fliesskommazahlen nicht exakt. Kritisch ist dabei oft nicht die absolute Genauigkeit, sondern dass der Algorithmus völlig falsche Ergebnisse liefern oder in eine unendliche Schleife laufen kann (z.B. Vorbeilaufen am Startpunkt, weil dieser doppelt auftritt).

Abhilfe: Programmbibliotheken mit exakten Datentypen (für spezielle Operationen).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: numerische Probleme.
Der Orientierungsausdruck \((r_x - q_x)(p_y - q_y) - (p_x - q_x)(r_y - q_y) > 0\) ist mit Fliesskommazahlen nicht exakt. Kritisch ist dabei oft nicht die absolute Genauigkeit, sondern dass der Algorithmus völlig falsche Ergebnisse liefern oder in eine unendliche Schleife laufen kann (z.B. Vorbeilaufen am Startpunkt, weil dieser doppelt auftritt).

Abhilfe: Programmbibliotheken mit exakten Datentypen (für spezielle Operationen).

After

Front

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: numerische Probleme.

Der Orientierungsausdruck \((r_x - q_x)(p_y - q_y) - (p_x - q_x)(r_y - q_y) > 0\) ist mit Fliesskommazahlen nicht exakt.

Kritisch ist dabei oft nicht die absolute Genauigkeit, sondern dass der Algorithmus völlig falsche Ergebnisse liefern oder in eine unendliche Schleife laufen kann (z.B. Vorbeilaufen am Startpunkt, weil dieser doppelt auftritt).

Abhilfe: Programmbibliotheken mit exakten Datentypen (für spezielle Operationen).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: numerische Probleme.

Der Orientierungsausdruck \((r_x - q_x)(p_y - q_y) - (p_x - q_x)(r_y - q_y) > 0\) ist mit Fliesskommazahlen nicht exakt.

Kritisch ist dabei oft nicht die absolute Genauigkeit, sondern dass der Algorithmus völlig falsche Ergebnisse liefern oder in eine unendliche Schleife laufen kann (z.B. Vorbeilaufen am Startpunkt, weil dieser doppelt auftritt).

Abhilfe: Programmbibliotheken mit exakten Datentypen (für spezielle Operationen).
Field-by-field Comparison
Field Before After
Text <b>JarvisWrap: numerische Probleme.</b><br>Der Orientierungsausdruck \((r_x - q_x)(p_y - q_y) - (p_x - q_x)(r_y - q_y) &gt; 0\) ist mit Fliesskommazahlen nicht exakt. Kritisch ist dabei oft nicht die absolute Genauigkeit, sondern dass der Algorithmus {{c1::völlig falsche Ergebnisse liefern oder in eine unendliche Schleife laufen}} kann (z.B. {{c2::Vorbeilaufen am Startpunkt}}, weil dieser doppelt auftritt).<br><br>Abhilfe: {{c3::Programmbibliotheken mit exakten Datentypen}} (für spezielle Operationen). <b>JarvisWrap: numerische Probleme.<br></b><br>Der Orientierungsausdruck \((r_x - q_x)(p_y - q_y) - (p_x - q_x)(r_y - q_y) &gt; 0\) ist mit Fliesskommazahlen nicht exakt. <br><br>Kritisch ist dabei oft nicht die absolute Genauigkeit, sondern dass der Algorithmus {{c1::völlig falsche Ergebnisse liefern oder in eine unendliche Schleife laufen kann (z.B. Vorbeilaufen am Startpunkt, weil dieser doppelt auftritt)}}.<br><br>Abhilfe: {{c2::Programmbibliotheken mit exakten Datentypen (für spezielle Operationen)}}.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 19: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Classic
GUID: [/jcw,k!?v
modified

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Lemma (Randkanten charakterisieren die Hülle).
Wann ist \((q_0, q_1, \ldots, q_{h-1})\) die Eckenfolge des \(\operatorname{conv}(P)\) umschliessenden Polygons gegen den Uhrzeigersinn? (Indizes \(\bmod\, h\))

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Lemma (Randkanten charakterisieren die Hülle).
Wann ist \((q_0, q_1, \ldots, q_{h-1})\) die Eckenfolge des \(\operatorname{conv}(P)\) umschliessenden Polygons gegen den Uhrzeigersinn? (Indizes \(\bmod\, h\))

Genau dann, wenn alle Paare \((q_{i-1}, q_i)\), \(i = 1, 2, \ldots, h\), Randkanten von \(P\) sind (Indizes \(\bmod\, h\)).

Das übersetzt die globale Eigenschaft "Eckenfolge der Hülle" in lokal prüfbare Randkanten-Bedingungen.

After

Front

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Wann ist \((q_0, q_1, \ldots, q_{h-1})\) die Eckenfolge des \(\operatorname{conv}(P)\) umschliessenden Polygons gegen den Uhrzeigersinn? (Indizes \(\bmod\, h\))

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Wann ist \((q_0, q_1, \ldots, q_{h-1})\) die Eckenfolge des \(\operatorname{conv}(P)\) umschliessenden Polygons gegen den Uhrzeigersinn? (Indizes \(\bmod\, h\))

Genau dann, wenn alle Paare \((q_{i-1}, q_i)\), \(i = 1, 2, \ldots, h\), Randkanten von \(P\) sind (Indizes \(\bmod\, h\)).



Das übersetzt die globale Eigenschaft "Eckenfolge der Hülle" in lokal prüfbare Randkanten-Bedingungen.
Field-by-field Comparison
Field Before After
Front <b>Lemma (Randkanten charakterisieren die Hülle).</b><br>Wann ist \((q_0, q_1, \ldots, q_{h-1})\) die Eckenfolge des \(\operatorname{conv}(P)\) umschliessenden Polygons gegen den Uhrzeigersinn? (Indizes \(\bmod\, h\)) Wann ist \((q_0, q_1, \ldots, q_{h-1})\) die Eckenfolge des \(\operatorname{conv}(P)\) umschliessenden Polygons gegen den Uhrzeigersinn? (Indizes \(\bmod\, h\))
Back <b>Genau dann, wenn</b> alle Paare \((q_{i-1}, q_i)\), \(i = 1, 2, \ldots, h\), <b>Randkanten von \(P\)</b> sind (Indizes \(\bmod\, h\)).<br><br>Das übersetzt die globale Eigenschaft "Eckenfolge der Hülle" in lokal prüfbare Randkanten-Bedingungen. <b>Genau dann, wenn</b> alle Paare \((q_{i-1}, q_i)\), \(i = 1, 2, \ldots, h\), <b>Randkanten von \(P\)</b> sind (Indizes \(\bmod\, h\)).<br><br><img src="paste-12efe5806bf069f8d56fa92f61f53fa07d83a93d.jpg"><br><br>Das übersetzt die globale Eigenschaft "Eckenfolge der Hülle" in lokal prüfbare Randkanten-Bedingungen.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 20: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: bX&z[6rdCT
modified

Before

Front

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Jarvis Wrap (Einwickeln).
Startend bei \(q_0\) (kleinste \(x\)-Koordinate) hängt man wiederholt {{c1::\(q_h \leftarrow \texttt{FindNext}(q_{h-1})\)}} an, bis \(q_h = q_0\) (die Hülle ist geschlossen):
JarvisWrap(P):
  q₀ ← Punkt in P mit kleinster x-Koordinate
  h ← 0
  repeat:
    h ← h + 1
    q_h ← FindNext(q_{h-1})
  until q_h = q₀
  return (q₀, q₁, ..., q_{h-1})

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Jarvis Wrap (Einwickeln).
Startend bei \(q_0\) (kleinste \(x\)-Koordinate) hängt man wiederholt {{c1::\(q_h \leftarrow \texttt{FindNext}(q_{h-1})\)}} an, bis \(q_h = q_0\) (die Hülle ist geschlossen):
JarvisWrap(P):
  q₀ ← Punkt in P mit kleinster x-Koordinate
  h ← 0
  repeat:
    h ← h + 1
    q_h ← FindNext(q_{h-1})
  until q_h = q₀
  return (q₀, q₁, ..., q_{h-1})

After

Front

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Jarvis Wrap (Einwickeln).
Startend bei \(q_0\) (kleinste \(x\)-Koordinate) hängt man wiederholt {{c1::\(q_h \leftarrow \texttt{FindNext}(q_{h-1})\)}} an, bis \(q_h = q_0\) (die Hülle ist geschlossen):

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Jarvis Wrap (Einwickeln).
Startend bei \(q_0\) (kleinste \(x\)-Koordinate) hängt man wiederholt {{c1::\(q_h \leftarrow \texttt{FindNext}(q_{h-1})\)}} an, bis \(q_h = q_0\) (die Hülle ist geschlossen):

Field-by-field Comparison
Field Before After
Text <b>Jarvis Wrap (Einwickeln).</b><br>Startend bei \(q_0\) (kleinste \(x\)-Koordinate) hängt man wiederholt {{c1::\(q_h \leftarrow \texttt{FindNext}(q_{h-1})\)}} an, bis {{c2::\(q_h = q_0\)}} (die Hülle ist geschlossen):<pre>JarvisWrap(P): q₀ ← Punkt in P mit kleinster x-Koordinate h ← 0 repeat: h ← h + 1 q_h ← FindNext(q_{h-1}) until q_h = q₀ return (q₀, q₁, ..., q_{h-1})</pre> <b>Jarvis Wrap (Einwickeln).</b><br>Startend bei \(q_0\) (kleinste \(x\)-Koordinate) hängt man wiederholt {{c1::\(q_h \leftarrow \texttt{FindNext}(q_{h-1})\)}} an, bis {{c1::\(q_h = q_0\)&nbsp;(die Hülle ist geschlossen)}}:
Extra <img src="paste-841acfd15a8aa5b7a755ae69555a2d6eb321e6d8.jpg">
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 21: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Classic
GUID: fXWJymWNSI
modified

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Satz: Laufzeit von JarvisWrap.
In welcher Zeit berechnet JarvisWrap die konvexe Hülle von \(n\) Punkten in allgemeiner Lage in \(\mathbb{R}^2\)?

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Satz: Laufzeit von JarvisWrap.
In welcher Zeit berechnet JarvisWrap die konvexe Hülle von \(n\) Punkten in allgemeiner Lage in \(\mathbb{R}^2\)?

In Zeit \(O(nh)\), wobei \(h\) die Anzahl der Ecken der konvexen Hülle von \(P\) ist.

Jeder der \(h\) FindNext-Aufrufe kostet \(O(n)\) (output-sensitiv).

After

Front

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
In welcher Zeit berechnet JarvisWrap die konvexe Hülle von \(n\) Punkten in allgemeiner Lage in \(\mathbb{R}^2\)?

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
In welcher Zeit berechnet JarvisWrap die konvexe Hülle von \(n\) Punkten in allgemeiner Lage in \(\mathbb{R}^2\)?

In Zeit \(O(nh)\), wobei \(h\) die Anzahl der Ecken der konvexen Hülle von \(P\) ist.

Jeder der \(h\) FindNext-Aufrufe kostet \(O(n)\) (output-sensitiv).
Field-by-field Comparison
Field Before After
Front <b>Satz: Laufzeit von JarvisWrap.</b><br>In welcher Zeit berechnet JarvisWrap die konvexe Hülle von \(n\) Punkten in allgemeiner Lage in \(\mathbb{R}^2\)? In welcher Zeit berechnet JarvisWrap die konvexe Hülle von \(n\) Punkten in allgemeiner Lage in \(\mathbb{R}^2\)?
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 22: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: g8$x7r++].
modified

Before

Front

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
LocalRepair: Laufzeitanalyse.
Start mit \(2(n-1)\) Ecken, Ende mit \(h\) Ecken, also genau \(2(n-1) - h = O(n)\) erfolgreiche (entfernende) Tests. Pro Punkt \(p_i\) gibt es zudem zwei erfolglose Tests (einmal unten, einmal oben).

Nach dem anfänglichen Sortieren in \(O(n \log n)\) ist die eigentliche Reparatur also \(O(n)\).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
LocalRepair: Laufzeitanalyse.
Start mit \(2(n-1)\) Ecken, Ende mit \(h\) Ecken, also genau \(2(n-1) - h = O(n)\) erfolgreiche (entfernende) Tests. Pro Punkt \(p_i\) gibt es zudem zwei erfolglose Tests (einmal unten, einmal oben).

Nach dem anfänglichen Sortieren in \(O(n \log n)\) ist die eigentliche Reparatur also \(O(n)\).

After

Front

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
LocalRepair: Laufzeitanalyse.
Start mit \(2(n-1)\) Ecken, Ende mit \(h\) Ecken, also genau \(2(n-1) - h = O(n)\) erfolgreiche (entfernende) Tests. Pro Punkt \(p_i\) gibt es zudem zwei erfolglose Tests (einmal unten, einmal oben).

Nach dem anfänglichen Sortieren in \(O(n \log n)\) ist die eigentliche Reparatur also \(O(n)\).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
LocalRepair: Laufzeitanalyse.
Start mit \(2(n-1)\) Ecken, Ende mit \(h\) Ecken, also genau \(2(n-1) - h = O(n)\) erfolgreiche (entfernende) Tests. Pro Punkt \(p_i\) gibt es zudem zwei erfolglose Tests (einmal unten, einmal oben).

Nach dem anfänglichen Sortieren in \(O(n \log n)\) ist die eigentliche Reparatur also \(O(n)\).
Field-by-field Comparison
Field Before After
Text <b>LocalRepair: Laufzeitanalyse.</b><br>Start mit \(2(n-1)\) Ecken, Ende mit \(h\) Ecken, also genau {{c1::\(2(n-1) - h = O(n)\)}} erfolgreiche (entfernende) Tests. Pro Punkt \(p_i\) gibt es zudem {{c2::zwei erfolglose Tests}} (einmal unten, einmal oben).<br><br>Nach dem anfänglichen Sortieren in \(O(n \log n)\) ist die eigentliche Reparatur also {{c3::\(O(n)\)}}. <b>LocalRepair: Laufzeitanalyse.</b><br>Start mit \(2(n-1)\) Ecken, Ende mit \(h\) Ecken, also genau {{c1::\(2(n-1) - h = O(n)\)}} erfolgreiche (entfernende) Tests. Pro Punkt \(p_i\) gibt es zudem {{c2::zwei erfolglose Tests (einmal unten, einmal oben)}}.<br><br>Nach dem anfänglichen Sortieren in \(O(n \log n)\) ist die eigentliche Reparatur also {{c1::\(O(n)\)}}.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 23: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: k!;R/,m=ac
modified

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Front

ETH::2._Semester::A&W::2._Wahrscheinlichkeitstheorie_und_randomisierte_Algorithmen::8._Randomisierte_Algorithmen::3._Primzahltest
Designziel für Primzahltests: Laufzeit polynomiell in \(\log n\) (Darstellungsgrösse). Naives Trial-Division bis \(\sqrt{n}\) ist zu langsam für \(n \approx 2^{1000}\).

Der \(\mathrm{ggT}\) zweier Zahlen \(m, n\) lässt sich mit dem Euklid-Algorithmus in \(O((\log nm)^3)\) berechnen. Damit:
Euklid-Primzahltest(n):
  wähle a ∈ [n-1] zufällig gleichverteilt
  if ggT(a, n) = 1: return 'Primzahl'
  else: return 'keine Primzahl'
Korrektheit:
  • Falls \(n\) prim: Ausgabe immer korrekt (alle \(a \in [n-1]\) sind teilerfremd zu \(n\)).
  • Falls \(n\) nicht prim: Falsche Ausgabe 'Primzahl' mit Wahrscheinlichkeit {{c3::\(\frac{|\mathbb{Z}_n^*|}{n-1}\)}}.

Back

ETH::2._Semester::A&W::2._Wahrscheinlichkeitstheorie_und_randomisierte_Algorithmen::8._Randomisierte_Algorithmen::3._Primzahltest
Designziel für Primzahltests: Laufzeit polynomiell in \(\log n\) (Darstellungsgrösse). Naives Trial-Division bis \(\sqrt{n}\) ist zu langsam für \(n \approx 2^{1000}\).

Der \(\mathrm{ggT}\) zweier Zahlen \(m, n\) lässt sich mit dem Euklid-Algorithmus in \(O((\log nm)^3)\) berechnen. Damit:
Euklid-Primzahltest(n):
  wähle a ∈ [n-1] zufällig gleichverteilt
  if ggT(a, n) = 1: return 'Primzahl'
  else: return 'keine Primzahl'
Korrektheit:
  • Falls \(n\) prim: Ausgabe immer korrekt (alle \(a \in [n-1]\) sind teilerfremd zu \(n\)).
  • Falls \(n\) nicht prim: Falsche Ausgabe 'Primzahl' mit Wahrscheinlichkeit {{c3::\(\frac{|\mathbb{Z}_n^*|}{n-1}\)}}.

Trivialerweise gilt: \(\mathrm{ggT}(a, n) > 1\) für ein \(a \in [n-1]\) \(\Rightarrow\) \(n\) nicht prim. Der Test sucht also einen kleinen gemeinsamen Faktor mit zufälligem \(a\).

Problem: für \(n = p^2\) ist die Fehlerrate \(\approx 1 - 1/\sqrt{n}\), also fast \(1\). Der Test ist deshalb in der Praxis nutzlos.

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ETH::2._Semester::A&W::2._Wahrscheinlichkeitstheorie_und_randomisierte_Algorithmen::8._Randomisierte_Algorithmen::3._Primzahltest
Designziel für Primzahltests: Laufzeit polynomiell in \(\log n\) (Darstellungsgrösse). Naives Trial-Division bis \(\sqrt{n}\) ist zu langsam für \(n \approx 2^{1000}\).

Der \(\mathrm{ggT}\) zweier Zahlen \(m, n\) lässt sich mit dem Euklid-Algorithmus in \(O((\log nm)^3)\) berechnen. Damit:



Korrektheit:
  • Falls \(n\) prim: Ausgabe immer korrekt (alle \(a \in [n-1]\) sind teilerfremd zu \(n\)).
  • Falls \(n\) nicht prim: Falsche Ausgabe 'Primzahl' mit Wahrscheinlichkeit {{c3::\(\frac{|\mathbb{Z}_n^*|}{n-1}\)}}.

Back

ETH::2._Semester::A&W::2._Wahrscheinlichkeitstheorie_und_randomisierte_Algorithmen::8._Randomisierte_Algorithmen::3._Primzahltest
Designziel für Primzahltests: Laufzeit polynomiell in \(\log n\) (Darstellungsgrösse). Naives Trial-Division bis \(\sqrt{n}\) ist zu langsam für \(n \approx 2^{1000}\).

Der \(\mathrm{ggT}\) zweier Zahlen \(m, n\) lässt sich mit dem Euklid-Algorithmus in \(O((\log nm)^3)\) berechnen. Damit:



Korrektheit:
  • Falls \(n\) prim: Ausgabe immer korrekt (alle \(a \in [n-1]\) sind teilerfremd zu \(n\)).
  • Falls \(n\) nicht prim: Falsche Ausgabe 'Primzahl' mit Wahrscheinlichkeit {{c3::\(\frac{|\mathbb{Z}_n^*|}{n-1}\)}}.

Trivialerweise gilt: \(\mathrm{ggT}(a, n) > 1\) für ein \(a \in [n-1]\) \(\Rightarrow\) \(n\) nicht prim. Der Test sucht also einen kleinen gemeinsamen Faktor mit zufälligem \(a\).

Problem: für \(n = p^2\) ist die Fehlerrate \(\approx 1 - 1/\sqrt{n}\), also fast \(1\). Der Test ist deshalb in der Praxis nutzlos.
Field-by-field Comparison
Field Before After
Text Designziel für Primzahltests: Laufzeit polynomiell in \(\log n\) (Darstellungsgrösse). Naives Trial-Division bis \(\sqrt{n}\) ist zu langsam für \(n \approx 2^{1000}\).<br><br>Der \(\mathrm{ggT}\) zweier Zahlen \(m, n\) lässt sich mit dem Euklid-Algorithmus in \(O({{c1::(\log nm)^3}})\)&nbsp;berechnen. Damit:<pre>Euklid-Primzahltest(n): wähle a ∈ [n-1] zufällig gleichverteilt if ggT(a, n) = 1: return 'Primzahl' else: return 'keine Primzahl'</pre>Korrektheit:<ul><li>Falls \(n\) prim: {{c2::Ausgabe immer korrekt (alle \(a \in [n-1]\) sind teilerfremd zu \(n\))}}.</li><li>Falls \(n\) nicht prim: Falsche Ausgabe 'Primzahl' mit Wahrscheinlichkeit {{c3::\(\frac{|\mathbb{Z}_n^*|}{n-1}\)}}.</li></ul> Designziel für Primzahltests: Laufzeit polynomiell in \(\log n\) (Darstellungsgrösse). Naives Trial-Division bis \(\sqrt{n}\) ist zu langsam für \(n \approx 2^{1000}\).<br><br>Der \(\mathrm{ggT}\) zweier Zahlen \(m, n\) lässt sich mit dem Euklid-Algorithmus in \(O({{c1::(\log nm)^3}})\)&nbsp;berechnen. Damit:<br><br><img src="paste-6f9413d03db5f86f9dbc5fa17bdff6435967627d.jpg"><br><br>Korrektheit:<ul><li>Falls \(n\) prim: {{c2::Ausgabe immer korrekt (alle \(a \in [n-1]\) sind teilerfremd zu \(n\))}}.</li><li>Falls \(n\) nicht prim: Falsche Ausgabe 'Primzahl' mit Wahrscheinlichkeit {{c3::\(\frac{|\mathbb{Z}_n^*|}{n-1}\)}}.</li></ul>
Tags: ETH::2._Semester::A&W::2._Wahrscheinlichkeitstheorie_und_randomisierte_Algorithmen::8._Randomisierte_Algorithmen::3._Primzahltest

Note 24: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: niQo~f{zrh
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
LocalRepair (Eingabe \((p_1, \ldots, p_n)\) nach \(x\)-Koordinate sortiert).
Zwei Sweeps: erst unterer Rand, links nach rechts, dann oberer Rand, rechts nach links; jeweils wird \(q_i\) per Pop entfernt, solange \(p_i\) rechts von \(q_{h-1}, q_h\) liegt:
LocalRepair(p₁, ..., p_n):   # sortiert
  q₀ ← p₁; h ← 0
  for i ← 2 to n:              # unterer Rand, links→rechts
    while h > 0 and p_i rechts von q_{h-1}, q_h:
      h ← h - 1
    h ← h + 1; q_h ← p_i
  h' ← h
  for i ← n-1 downto 1:        # oberer Rand, rechts→links
    while h > h' and p_i rechts von q_{h-1}, q_h:
      h ← h - 1
    h ← h + 1; q_h ← p_i
  return (q₀, q₁, ..., q_{h-1})

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
LocalRepair (Eingabe \((p_1, \ldots, p_n)\) nach \(x\)-Koordinate sortiert).
Zwei Sweeps: erst unterer Rand, links nach rechts, dann oberer Rand, rechts nach links; jeweils wird \(q_i\) per Pop entfernt, solange \(p_i\) rechts von \(q_{h-1}, q_h\) liegt:
LocalRepair(p₁, ..., p_n):   # sortiert
  q₀ ← p₁; h ← 0
  for i ← 2 to n:              # unterer Rand, links→rechts
    while h > 0 and p_i rechts von q_{h-1}, q_h:
      h ← h - 1
    h ← h + 1; q_h ← p_i
  h' ← h
  for i ← n-1 downto 1:        # oberer Rand, rechts→links
    while h > h' and p_i rechts von q_{h-1}, q_h:
      h ← h - 1
    h ← h + 1; q_h ← p_i
  return (q₀, q₁, ..., q_{h-1})

Nach der ersten Schleife ist \((q_0, \ldots, q_h)\) die untere konvexe Hülle von \(\{p_1, \ldots, p_n\}\); die Schranke \(h > h'\) verhindert, dass der obere Sweep in den unteren Rand hineinläuft.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
LocalRepair (Eingabe \((p_1, \ldots, p_n)\) nach \(x\)-Koordinate sortiert).
Zwei Sweeps: erst unterer Rand, links nach rechts, dann oberer Rand, rechts nach links; jeweils wird \(q_i\) per Pop entfernt, solange \(p_i\) rechts von \(q_{h-1}, q_h\) liegt:

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
LocalRepair (Eingabe \((p_1, \ldots, p_n)\) nach \(x\)-Koordinate sortiert).
Zwei Sweeps: erst unterer Rand, links nach rechts, dann oberer Rand, rechts nach links; jeweils wird \(q_i\) per Pop entfernt, solange \(p_i\) rechts von \(q_{h-1}, q_h\) liegt:


Nach der ersten Schleife ist \((q_0, \ldots, q_h)\) die untere konvexe Hülle von \(\{p_1, \ldots, p_n\}\); die Schranke \(h > h'\) verhindert, dass der obere Sweep in den unteren Rand hineinläuft.
Field-by-field Comparison
Field Before After
Text <b>LocalRepair</b> (Eingabe \((p_1, \ldots, p_n)\) nach \(x\)-Koordinate sortiert).<br>Zwei Sweeps: erst {{c1::unterer Rand, links nach rechts}}, dann {{c2::oberer Rand, rechts nach links}}; jeweils wird \(q_i\) per Pop entfernt, solange \(p_i\) rechts von \(q_{h-1}, q_h\) liegt:<pre>LocalRepair(p₁, ..., p_n): # sortiert q₀ ← p₁; h ← 0 for i ← 2 to n: # unterer Rand, links→rechts while h &gt; 0 and p_i rechts von q_{h-1}, q_h: h ← h - 1 h ← h + 1; q_h ← p_i h' ← h for i ← n-1 downto 1: # oberer Rand, rechts→links while h &gt; h' and p_i rechts von q_{h-1}, q_h: h ← h - 1 h ← h + 1; q_h ← p_i return (q₀, q₁, ..., q_{h-1})</pre> <b>LocalRepair</b> (Eingabe \((p_1, \ldots, p_n)\) nach \(x\)-Koordinate sortiert).<br>Zwei Sweeps: erst {{c1::unterer Rand, links nach rechts}}, dann {{c1::oberer Rand, rechts nach links}}; jeweils wird \(q_i\) per Pop entfernt, solange \(p_i\) rechts von \(q_{h-1}, q_h\) liegt:<br><br><img src="paste-42be178c67df8469988fbf9c0a012b8a4d83abde.jpg">
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 25: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: qzy.kvo
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: Umgang mit Degeneriertheiten (Kollinearitäten, gleiche \(x\)-Koordinaten, Duplikate).
  • Startpunkt \(q_0\): nimm den Punkt mit lexikographisch kleinster Koordinate (unter kleinster \(x\)-Koordinate den mit kleinster \(y\)-Koordinate).
  • Test "\(p\) rechts von \(q, q_{\text{next} }\)" ersetzen durch: rechts von \(q, q_{\text{next} }\) {{c2::oder (\(p\) auf der Geraden durch \(q, q_{\text{next} }\) und \(|qp| > |q q_{\text{next} }|\))}}.
  • Punkte sind i.d.R. nicht einmal verschieden (z.B. in einem Feld gegeben).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: Umgang mit Degeneriertheiten (Kollinearitäten, gleiche \(x\)-Koordinaten, Duplikate).
  • Startpunkt \(q_0\): nimm den Punkt mit lexikographisch kleinster Koordinate (unter kleinster \(x\)-Koordinate den mit kleinster \(y\)-Koordinate).
  • Test "\(p\) rechts von \(q, q_{\text{next} }\)" ersetzen durch: rechts von \(q, q_{\text{next} }\) {{c2::oder (\(p\) auf der Geraden durch \(q, q_{\text{next} }\) und \(|qp| > |q q_{\text{next} }|\))}}.
  • Punkte sind i.d.R. nicht einmal verschieden (z.B. in einem Feld gegeben).

Software ohne Berücksichtigung dieser Fälle hat geringen praktischen Nutzen.

After

Front

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: Umgang mit Degeneriertheiten (Kollinearitäten, gleiche \(x\)-Koordinaten, Duplikate).
  • Startpunkt \(q_0\): nimm den Punkt mit lexikographisch kleinster Koordinate (unter kleinster \(x\)-Koordinate den mit kleinster \(y\)-Koordinate).
  • Test "\(p\) rechts von \(q, q_{\text{next} }\)" ersetzen durch: {{c2::rechts von \(q, q_{\text{next} }\) oder (\(p\) auf der Geraden durch \(q, q_{\text{next} }\) und \(|qp| > |q q_{\text{next} }|\))}}.
  • Punkte sind i.d.R. nicht einmal verschieden (z.B. in einem Feld gegeben).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: Umgang mit Degeneriertheiten (Kollinearitäten, gleiche \(x\)-Koordinaten, Duplikate).
  • Startpunkt \(q_0\): nimm den Punkt mit lexikographisch kleinster Koordinate (unter kleinster \(x\)-Koordinate den mit kleinster \(y\)-Koordinate).
  • Test "\(p\) rechts von \(q, q_{\text{next} }\)" ersetzen durch: {{c2::rechts von \(q, q_{\text{next} }\) oder (\(p\) auf der Geraden durch \(q, q_{\text{next} }\) und \(|qp| > |q q_{\text{next} }|\))}}.
  • Punkte sind i.d.R. nicht einmal verschieden (z.B. in einem Feld gegeben).

Software ohne Berücksichtigung dieser Fälle hat geringen praktischen Nutzen.
Field-by-field Comparison
Field Before After
Text <b>JarvisWrap: Umgang mit Degeneriertheiten</b> (Kollinearitäten, gleiche \(x\)-Koordinaten, Duplikate).<br><ul><li>Startpunkt \(q_0\): nimm den Punkt mit {{c1::lexikographisch kleinster Koordinate}} (unter kleinster \(x\)-Koordinate den mit kleinster \(y\)-Koordinate).</li><li>Test "\(p\) rechts von \(q, q_{\text{next} }\)" ersetzen durch: rechts von \(q, q_{\text{next} }\) {{c2::oder (\(p\) auf der Geraden durch \(q, q_{\text{next} }\) und \(|qp| &gt; |q q_{\text{next} }|\))}}.</li><li>Punkte sind i.d.R. {{c3::nicht einmal verschieden}} (z.B. in einem Feld gegeben).</li></ul> <b>JarvisWrap: Umgang mit Degeneriertheiten</b> (Kollinearitäten, gleiche \(x\)-Koordinaten, Duplikate).<br><ul><li>Startpunkt \(q_0\): nimm den Punkt mit {{c1::lexikographisch kleinster Koordinate (unter kleinster \(x\)-Koordinate den mit kleinster \(y\)-Koordinate)}}.</li><li>Test "\(p\) rechts von \(q, q_{\text{next} }\)" ersetzen durch: {{c2::rechts von \(q, q_{\text{next} }\)&nbsp;oder (\(p\) auf der Geraden durch \(q, q_{\text{next} }\) und \(|qp| &gt; |q q_{\text{next} }|\))}}.</li><li>Punkte sind i.d.R. {{c3::nicht einmal verschieden (z.B. in einem Feld gegeben)}}.</li></ul>
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 26: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: smm|mYgkUr
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: Laufzeit-Spezialfälle.
Aus \(O(nh)\) folgt:
  • Da \(h \leq n\), läuft JarvisWrap in \(O(n^2)\) (statt \(O(n^3)\) beim naiven Ansatz).
  • Ist \(h = O(1)\) (z.B. \(\operatorname{conv}(P)\) ein Dreieck), so \(O(n)\).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: Laufzeit-Spezialfälle.
Aus \(O(nh)\) folgt:
  • Da \(h \leq n\), läuft JarvisWrap in \(O(n^2)\) (statt \(O(n^3)\) beim naiven Ansatz).
  • Ist \(h = O(1)\) (z.B. \(\operatorname{conv}(P)\) ein Dreieck), so \(O(n)\).

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: Laufzeit-Spezialfälle.
Aus \(O(nh)\) folgt:
  • Da \(h \leq n\), läuft JarvisWrap in \(O(n^2)\) (statt \(O(n^3)\) beim naiven Ansatz).
  • Ist \(h = O(1)\) (z.B. \(\operatorname{conv}(P)\) ein Dreieck), so \(O(n)\).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
JarvisWrap: Laufzeit-Spezialfälle.
Aus \(O(nh)\) folgt:
  • Da \(h \leq n\), läuft JarvisWrap in \(O(n^2)\) (statt \(O(n^3)\) beim naiven Ansatz).
  • Ist \(h = O(1)\) (z.B. \(\operatorname{conv}(P)\) ein Dreieck), so \(O(n)\).
Field-by-field Comparison
Field Before After
Text <b>JarvisWrap: Laufzeit-Spezialfälle.</b><br>Aus \(O(nh)\) folgt:<br><ul><li>Da \(h \leq n\), läuft JarvisWrap in {{c1::\(O(n^2)\)}} (statt \(O(n^3)\) beim naiven Ansatz).</li><li>Ist \(h = O(1)\) (z.B. \(\operatorname{conv}(P)\) ein Dreieck), so {{c2::\(O(n)\)}}.</li></ul> <b>JarvisWrap: Laufzeit-Spezialfälle.</b><br>Aus \(O(nh)\) folgt:<br><ul><li>Da \(h \leq n\), läuft JarvisWrap in {{c1::\(O(n^2)\)&nbsp;(statt \(O(n^3)\) beim naiven Ansatz)}}.</li><li>Ist \(h = O(1)\) (z.B. \(\operatorname{conv}(P)\) ein Dreieck), so {{c2::\(O(n)\)}}.</li></ul>
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 27: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: tJY%fGS%zk
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::3._Clarkson-Algorithmus
Anmerkungen zum Clarkson-Algorithmus.
  • Der Algorithmus funktioniert auch für die kleinste umschliessende Kugel (oder Ellipse) in allen Dimensionen, mit anderen Konstanten statt der \(11\). Bei fixer Dimension bleibt die Laufzeit \(O(n \log n)\).
  • Es gibt auch einfache randomisierte und sogar deterministische Linearzeit-Algorithmen (in jeder fixen Dimension).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::3._Clarkson-Algorithmus
Anmerkungen zum Clarkson-Algorithmus.
  • Der Algorithmus funktioniert auch für die kleinste umschliessende Kugel (oder Ellipse) in allen Dimensionen, mit anderen Konstanten statt der \(11\). Bei fixer Dimension bleibt die Laufzeit \(O(n \log n)\).
  • Es gibt auch einfache randomisierte und sogar deterministische Linearzeit-Algorithmen (in jeder fixen Dimension).

Idee von [Clarkson '95].

After

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::3._Clarkson-Algorithmus
Anmerkungen zum Clarkson-Algorithmus.
  • Der Algorithmus funktioniert auch für die kleinste umschliessende Kugel (oder Ellipse) in allen Dimensionen, mit anderen Konstanten statt der \(11\). Bei fixer Dimension bleibt die Laufzeit \(O(n \log n)\).
  • Es gibt auch einfache randomisierte und sogar deterministische Linearzeit-Algorithmen (in jeder fixen Dimension).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::3._Clarkson-Algorithmus
Anmerkungen zum Clarkson-Algorithmus.
  • Der Algorithmus funktioniert auch für die kleinste umschliessende Kugel (oder Ellipse) in allen Dimensionen, mit anderen Konstanten statt der \(11\). Bei fixer Dimension bleibt die Laufzeit \(O(n \log n)\).
  • Es gibt auch einfache randomisierte und sogar deterministische Linearzeit-Algorithmen (in jeder fixen Dimension).

Idee von [Clarkson '95].
Field-by-field Comparison
Field Before After
Text <b>Anmerkungen zum Clarkson-Algorithmus.</b><br><ul><li>Der Algorithmus funktioniert auch für die kleinste umschliessende Kugel (oder Ellipse) in {{c1::allen Dimensionen}}, mit anderen Konstanten statt der \(11\). Bei {{c2::fixer Dimension}} bleibt die Laufzeit \(O(n \log n)\).</li><li>Es gibt auch einfache randomisierte und sogar deterministische {{c3::Linearzeit}}-Algorithmen (in jeder fixen Dimension).</li></ul> <b>Anmerkungen zum Clarkson-Algorithmus.</b><br><ul><li>Der Algorithmus funktioniert auch für die kleinste umschliessende Kugel (oder Ellipse) in {{c1::allen Dimensionen}}, mit anderen Konstanten statt der \(11\). Bei {{c1::fixer Dimension}} bleibt die Laufzeit \(O(n \log n)\).</li><li>Es gibt auch einfache randomisierte und sogar deterministische {{c2::Linearzeit}}-Algorithmen (in jeder fixen Dimension).</li></ul>
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::3._Clarkson-Algorithmus

Note 28: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: v%M$D/Lp:4
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Zählen erreichbarer Knoten (gerichtet): Laufzeit
Für einen einzelnen Startknoten \(s\) bestimmt ein DFS/BFS die Anzahl erreichbarer Knoten in Zeit \(O(n + m)\).
Für alle Knoten ergibt das \(O(n(n + m))\).

Geht es schneller? Vermutlich nicht: Ein \(O(n^{0.99}(n+m))\)-Algorithmus würde \(k\)-SAT in \(O(1.999^n)\) lösen und damit der starken Exponentialzeithypothese (SETH) widersprechen.

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Zählen erreichbarer Knoten (gerichtet): Laufzeit
Für einen einzelnen Startknoten \(s\) bestimmt ein DFS/BFS die Anzahl erreichbarer Knoten in Zeit \(O(n + m)\).
Für alle Knoten ergibt das \(O(n(n + m))\).

Geht es schneller? Vermutlich nicht: Ein \(O(n^{0.99}(n+m))\)-Algorithmus würde \(k\)-SAT in \(O(1.999^n)\) lösen und damit der starken Exponentialzeithypothese (SETH) widersprechen.
Field-by-field Comparison
Field Before After
Text <b>Zählen erreichbarer Knoten (gerichtet): Laufzeit</b><br>Für einen <b>einzelnen</b> Startknoten \(s\) bestimmt ein DFS/BFS die Anzahl erreichbarer Knoten in Zeit \({{c1::O(n + m)}}\).<br>Für <b>alle</b> Knoten ergibt das \({{c2::O(n(n + m))}}\).<br><br>Geht es schneller? {{c3::Vermutlich nicht}}: Ein \(O(n^{0.99}(n+m))\)-Algorithmus würde \(k\)-SAT in \(O(1.999^n)\) lösen und damit der {{c4::starken Exponentialzeithypothese (SETH)}} widersprechen.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 29: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Classic
GUID: vr2QG*.a{<
modified

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::5._Laufzeitanalyse
Satz (Clarkson-Algorithmus).
Welche erwartete Laufzeit hat der Algorithmus, und wie folgt sie aus \(\Pr[T \geq k] \leq 0.993^k n\)?

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::5._Laufzeitanalyse
Satz (Clarkson-Algorithmus).
Welche erwartete Laufzeit hat der Algorithmus, und wie folgt sie aus \(\Pr[T \geq k] \leq 0.993^k n\)?

Der Algorithmus berechnet \(C(P)\) in erwartet \(O(n \log n)\) Zeit.

Proof Included. Die Laufzeit ist \(O(nT)\). Setze \(k_0 := \lfloor -\log_{0.993} n \rfloor = O(\log n)\). Dann\[\begin{gathered}\mathbb{E}[T] = \sum_{k \geq 1} \Pr[T \geq k] \;\leq\; \sum_{k=1}^{k_0} 1 \;+\; \sum_{k > k_0} 0.993^{\,k} n \\= k_0 \;+\; \underbrace{\sum_{k' \geq 0} 0.993^{\,k'} \cdot 0.993^{\,k_0 + 1} n}_{\leq\, O(1)} \;=\; k_0 + O(1) = O(\log n).\end{gathered}\]Also \(\mathbb{E}[\text{Laufzeit}] = O(n \cdot \mathbb{E}[T]) = O(n \log n)\).

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::5._Laufzeitanalyse
Clarkson-Algorithmus.
Welche erwartete Laufzeit hat der Algorithmus, und wie folgt sie aus \(\Pr[T \geq k] \leq 0.993^k n\)?

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::5._Laufzeitanalyse
Clarkson-Algorithmus.
Welche erwartete Laufzeit hat der Algorithmus, und wie folgt sie aus \(\Pr[T \geq k] \leq 0.993^k n\)?

Der Algorithmus berechnet \(C(P)\) in erwartet \(O(n \log n)\) Zeit.

Die Laufzeit ist \(O(nT)\). Setze \(k_0 := \lfloor -\log_{0.993} n \rfloor = O(\log n)\). Dann\[\begin{gathered}\mathbb{E}[T] = \sum_{k \geq 1} \Pr[T \geq k] \;\leq\; \sum_{k=1}^{k_0} 1 \;+\; \sum_{k > k_0} 0.993^{\,k} n \\= k_0 \;+\; \underbrace{\sum_{k' \geq 0} 0.993^{\,k'} \cdot 0.993^{\,k_0 + 1} n}_{\leq\, O(1)} \;=\; k_0 + O(1) = O(\log n).\end{gathered}\]Also \(\mathbb{E}[\text{Laufzeit}] = O(n \cdot \mathbb{E}[T]) = O(n \log n)\).
Field-by-field Comparison
Field Before After
Front <b>Satz (Clarkson-Algorithmus).</b><br>Welche erwartete Laufzeit hat der Algorithmus, und wie folgt sie aus \(\Pr[T \geq k] \leq 0.993^k n\)? <b>Clarkson-Algorithmus.</b><br>Welche erwartete Laufzeit hat der Algorithmus, und wie folgt sie aus \(\Pr[T \geq k] \leq 0.993^k n\)?
Back Der Algorithmus berechnet \(C(P)\) in erwartet \(O(n \log n)\) Zeit.<br><br>Proof Included. Die Laufzeit ist \(O(nT)\). Setze \(k_0 := \lfloor -\log_{0.993} n \rfloor = O(\log n)\). Dann\[\begin{gathered}\mathbb{E}[T] = \sum_{k \geq 1} \Pr[T \geq k] \;\leq\; \sum_{k=1}^{k_0} 1 \;+\; \sum_{k &gt; k_0} 0.993^{\,k} n \\= k_0 \;+\; \underbrace{\sum_{k' \geq 0} 0.993^{\,k'} \cdot 0.993^{\,k_0 + 1} n}_{\leq\, O(1)} \;=\; k_0 + O(1) = O(\log n).\end{gathered}\]Also \(\mathbb{E}[\text{Laufzeit}] = O(n \cdot \mathbb{E}[T]) = O(n \log n)\). Der Algorithmus berechnet \(C(P)\) in erwartet \(O(n \log n)\) Zeit.<br><br>Die Laufzeit ist \(O(nT)\). Setze \(k_0 := \lfloor -\log_{0.993} n \rfloor = O(\log n)\). Dann\[\begin{gathered}\mathbb{E}[T] = \sum_{k \geq 1} \Pr[T \geq k] \;\leq\; \sum_{k=1}^{k_0} 1 \;+\; \sum_{k &gt; k_0} 0.993^{\,k} n \\= k_0 \;+\; \underbrace{\sum_{k' \geq 0} 0.993^{\,k'} \cdot 0.993^{\,k_0 + 1} n}_{\leq\, O(1)} \;=\; k_0 + O(1) = O(\log n).\end{gathered}\]Also \(\mathbb{E}[\text{Laufzeit}] = O(n \cdot \mathbb{E}[T]) = O(n \log n)\).
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::5._Laufzeitanalyse

Note 30: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: x$AVm(?T-w
modified

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::5._Laufzeitanalyse
Schranke für \(\Pr[T \geq k]\).
Sei \(T\) die Rundenzahl und \(X_k = |P'|\) nach \(\min\{T, k\}\) Runden. Aus \(X_k \geq 2^{k/3}\) (falls \(T \geq k\)) und \(\mathbb{E}[X_k] \leq (\tfrac54)^k n\) folgt\[2^{k/3} \Pr[T \geq k] \;\leq\; \mathbb{E}[X_k] \;\leq\; \left(\tfrac54\right)^k n,\]also\[\Pr[T \geq k] \;\leq\; {{c1::\left(\frac{5}{4 \cdot 2^{1/3}}\right)^k n \;\leq\; 0.993^{\,k}\, n}}.\]

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::5._Laufzeitanalyse
Schranke für \(\Pr[T \geq k]\).
Sei \(T\) die Rundenzahl und \(X_k = |P'|\) nach \(\min\{T, k\}\) Runden. Aus \(X_k \geq 2^{k/3}\) (falls \(T \geq k\)) und \(\mathbb{E}[X_k] \leq (\tfrac54)^k n\) folgt\[2^{k/3} \Pr[T \geq k] \;\leq\; \mathbb{E}[X_k] \;\leq\; \left(\tfrac54\right)^k n,\]also\[\Pr[T \geq k] \;\leq\; {{c1::\left(\frac{5}{4 \cdot 2^{1/3}}\right)^k n \;\leq\; 0.993^{\,k}\, n}}.\]

Der entscheidende Schritt: \(\mathbb{E}[X_k] \geq \mathbb{E}[X_k \mid T \geq k]\cdot \Pr[T \geq k] \geq 2^{k/3}\Pr[T \geq k]\). Für \(k \geq -\log_{0.993} n\) wird die Schranke \(\leq 1\).

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::5._Laufzeitanalyse
Schranke für \(\Pr[T \geq k]\).
Sei \(T\) die Rundenzahl und \(X_k = |P'|\) nach \(\min\{T, k\}\) Runden. Aus \(X_k \geq 2^{k/3}\) (falls \(T \geq k\)) und \(\mathbb{E}[X_k] \leq (\tfrac54)^k n\) folgt\[2^{k/3} \Pr[T \geq k] \;\leq\; \mathbb{E}[X_k] \;\leq\; \left(\tfrac54\right)^k n,\]also\[\Pr[T \geq k] \;\leq\; {{c1::\left(\frac{5}{4 \cdot 2^{1/3} }\right)^k n \;\leq\; 0.993^{\,k}\, n}}.\]

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::5._Laufzeitanalyse
Schranke für \(\Pr[T \geq k]\).
Sei \(T\) die Rundenzahl und \(X_k = |P'|\) nach \(\min\{T, k\}\) Runden. Aus \(X_k \geq 2^{k/3}\) (falls \(T \geq k\)) und \(\mathbb{E}[X_k] \leq (\tfrac54)^k n\) folgt\[2^{k/3} \Pr[T \geq k] \;\leq\; \mathbb{E}[X_k] \;\leq\; \left(\tfrac54\right)^k n,\]also\[\Pr[T \geq k] \;\leq\; {{c1::\left(\frac{5}{4 \cdot 2^{1/3} }\right)^k n \;\leq\; 0.993^{\,k}\, n}}.\]

Der entscheidende Schritt: \(\mathbb{E}[X_k] \geq \mathbb{E}[X_k \mid T \geq k]\cdot \Pr[T \geq k] \geq 2^{k/3}\Pr[T \geq k]\). Für \(k \geq -\log_{0.993} n\) wird die Schranke \(\leq 1\).
Field-by-field Comparison
Field Before After
Text <b>Schranke für \(\Pr[T \geq k]\).</b><br>Sei \(T\) die Rundenzahl und \(X_k = |P'|\) nach \(\min\{T, k\}\) Runden. Aus \(X_k \geq 2^{k/3}\) (falls \(T \geq k\)) und \(\mathbb{E}[X_k] \leq (\tfrac54)^k n\) folgt\[2^{k/3} \Pr[T \geq k] \;\leq\; \mathbb{E}[X_k] \;\leq\; \left(\tfrac54\right)^k n,\]also\[\Pr[T \geq k] \;\leq\; {{c1::\left(\frac{5}{4 \cdot 2^{1/3}}\right)^k n \;\leq\; 0.993^{\,k}\, n}}.\] <b>Schranke für \(\Pr[T \geq k]\).</b><br>Sei \(T\) die Rundenzahl und \(X_k = |P'|\) nach \(\min\{T, k\}\) Runden. Aus \(X_k \geq 2^{k/3}\) (falls \(T \geq k\)) und \(\mathbb{E}[X_k] \leq (\tfrac54)^k n\) folgt\[2^{k/3} \Pr[T \geq k] \;\leq\; \mathbb{E}[X_k] \;\leq\; \left(\tfrac54\right)^k n,\]also\[\Pr[T \geq k] \;\leq\; {{c1::\left(\frac{5}{4 \cdot 2^{1/3} }\right)^k n \;\leq\; 0.993^{\,k}\, n}}.\]
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::4._Kleinster_umschliessender_Kreis::5._Laufzeitanalyse

Note 31: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: xHPCu-
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Zählen erreichbarer Knoten (ungerichtet)
Gegeben ein ungerichteter Graph \(G\), bestimme für jeden Knoten \(v\) die Anzahl erreichbarer Knoten.

Idee: Berechne mit DFS die Zusammenhangskomponenten; die Antwort für \(v\) ist dann die Grösse der Komponente von \(v\).
Laufzeit: \(O(n + m)\).

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
Zählen erreichbarer Knoten (ungerichtet)
Gegeben ein ungerichteter Graph \(G\), bestimme für jeden Knoten \(v\) die Anzahl erreichbarer Knoten.

Idee: Berechne mit DFS die Zusammenhangskomponenten; die Antwort für \(v\) ist dann die Grösse der Komponente von \(v\).
Laufzeit: \(O(n + m)\).

Konkret markiert ConnectedComponents jede Komponente mit einer eigenen Zahl, danach zählt man die Komponentengrössen \(\mathrm{cnt}[c]\) und setzt \(\mathrm{res}[v] = \mathrm{cnt}[\mathrm{comp}[v]]\).
Field-by-field Comparison
Field Before After
Text <b>Zählen erreichbarer Knoten (ungerichtet)</b><br>Gegeben ein ungerichteter Graph \(G\), bestimme für jeden Knoten \(v\) die Anzahl erreichbarer Knoten.<br><br>Idee: Berechne mit DFS die {{c1::Zusammenhangskomponenten}}; die Antwort für \(v\) ist dann die {{c2::Grösse der Komponente von \(v\)}}.<br>Laufzeit: \({{c3::O(n + m)}}\).
Extra Konkret markiert <code>ConnectedComponents</code> jede Komponente mit einer eigenen Zahl, danach zählt man die Komponentengrössen \(\mathrm{cnt}[c]\) und setzt \(\mathrm{res}[v] = \mathrm{cnt}[\mathrm{comp}[v]]\).
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 32: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: zks9N%wc9R
modified

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
ConvexHull-Problem.
Gegeben eine endliche Punktmenge {{c1::\(P \subseteq \mathbb{R}^2\)}}, bestimme die konvexe Hülle von \(P\).

In der Praxis heisst das konkret: bestimme {{c3::die Ecken des \(\operatorname{conv}(P)\) umrandenden Polygons, in der Reihenfolge gegen den Uhrzeigersinn}}.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
ConvexHull-Problem.
Gegeben eine endliche Punktmenge {{c1::\(P \subseteq \mathbb{R}^2\)}}, bestimme die konvexe Hülle von \(P\).

In der Praxis heisst das konkret: bestimme {{c3::die Ecken des \(\operatorname{conv}(P)\) umrandenden Polygons, in der Reihenfolge gegen den Uhrzeigersinn}}.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
ConvexHull-Problem.
Gegeben {{c1::eine endliche Punktmenge \(P \subseteq \mathbb{R}^2\)}}, bestimme die konvexe Hülle von \(P\).

In der Praxis heisst das konkret: bestimme {{c2::die Ecken des \(\operatorname{conv}(P)\) umrandenden Polygons, in der Reihenfolge gegen den Uhrzeigersinn}}.

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
ConvexHull-Problem.
Gegeben {{c1::eine endliche Punktmenge \(P \subseteq \mathbb{R}^2\)}}, bestimme die konvexe Hülle von \(P\).

In der Praxis heisst das konkret: bestimme {{c2::die Ecken des \(\operatorname{conv}(P)\) umrandenden Polygons, in der Reihenfolge gegen den Uhrzeigersinn}}.

Field-by-field Comparison
Field Before After
Text <b>ConvexHull-Problem.</b><br>Gegeben eine endliche Punktmenge {{c1::\(P \subseteq \mathbb{R}^2\)}}, bestimme {{c2::die konvexe Hülle von \(P\)}}.<br><br>In der Praxis heisst das konkret: bestimme {{c3::die Ecken des \(\operatorname{conv}(P)\) umrandenden Polygons, in der Reihenfolge gegen den Uhrzeigersinn}}. <b>ConvexHull-Problem.</b><br>Gegeben {{c1::eine endliche Punktmenge \(P \subseteq \mathbb{R}^2\)}}, bestimme die konvexe Hülle von \(P\).<br><br>In der Praxis heisst das konkret: bestimme {{c2::die Ecken des \(\operatorname{conv}(P)\) umrandenden Polygons, in der Reihenfolge gegen den Uhrzeigersinn}}.
Extra <img src="paste-8002da00026a8f6be826295cca0f4de33b7e29e4.jpg">
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 33: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: zni~6&*S9I
modified

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Startpunkt und FindNext.
Wähle \(q_0 :=\) Punkt mit kleinster \(x\)-Koordinate in \(P\); dieser ist sicher eine Ecke der konvexen Hülle.

FindNext(q) findet den nächsten Hüllenpunkt, indem es startend mit beliebigem \(p_0\) jeden Punkt durchgeht und \(q_{\text{next} }\) ersetzt, sobald {{c3::\(p\) rechts von \(q, q_{\text{next} }\) liegt}}:
FindNext(q):
  wähle p₀ ∈ P \ {q} beliebig
  q_next ← p₀
  for all p ∈ P \ {q, p₀}:
    if p rechts von q, q_next:
      q_next ← p
  return q_next

Back

ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Startpunkt und FindNext.
Wähle \(q_0 :=\) Punkt mit kleinster \(x\)-Koordinate in \(P\); dieser ist sicher eine Ecke der konvexen Hülle.

FindNext(q) findet den nächsten Hüllenpunkt, indem es startend mit beliebigem \(p_0\) jeden Punkt durchgeht und \(q_{\text{next} }\) ersetzt, sobald {{c3::\(p\) rechts von \(q, q_{\text{next} }\) liegt}}:
FindNext(q):
  wähle p₀ ∈ P \ {q} beliebig
  q_next ← p₀
  for all p ∈ P \ {q, p₀}:
    if p rechts von q, q_next:
      q_next ← p
  return q_next

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Startpunkt und FindNext.
Wähle \(q_0 :=\) Punkt mit kleinster \(x\)-Koordinate in \(P\); dieser ist sicher eine Ecke der konvexen Hülle.

FindNext(q) findet den nächsten Hüllenpunkt, indem es startend mit beliebigem \(p_0\) jeden Punkt durchgeht und \(q_{\text{next} }\) ersetzt, sobald {{c3::\(p\) rechts von \(q, q_{\text{next} }\) liegt}}:

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Startpunkt und FindNext.
Wähle \(q_0 :=\) Punkt mit kleinster \(x\)-Koordinate in \(P\); dieser ist sicher eine Ecke der konvexen Hülle.

FindNext(q) findet den nächsten Hüllenpunkt, indem es startend mit beliebigem \(p_0\) jeden Punkt durchgeht und \(q_{\text{next} }\) ersetzt, sobald {{c3::\(p\) rechts von \(q, q_{\text{next} }\) liegt}}:


Field-by-field Comparison
Field Before After
Text <b>Startpunkt und FindNext.</b><br>Wähle \(q_0 :=\) {{c1::Punkt mit kleinster \(x\)-Koordinate in \(P\)}}; dieser ist sicher {{c2::eine Ecke der konvexen Hülle}}.<br><br><code>FindNext(q)</code> findet den nächsten Hüllenpunkt, indem es startend mit beliebigem \(p_0\) jeden Punkt durchgeht und \(q_{\text{next} }\) ersetzt, sobald {{c3::\(p\) rechts von \(q, q_{\text{next} }\) liegt}}:<pre>FindNext(q): wähle p₀ ∈ P \ {q} beliebig q_next ← p₀ for all p ∈ P \ {q, p₀}: if p rechts von q, q_next: q_next ← p return q_next</pre> <b>Startpunkt und FindNext.</b><br>Wähle \(q_0 :=\) {{c1::Punkt mit kleinster \(x\)-Koordinate in \(P\)}}; dieser ist sicher {{c2::eine Ecke der konvexen Hülle}}.<br><br><code>FindNext(q)</code> findet den nächsten Hüllenpunkt, indem es startend mit beliebigem \(p_0\) jeden Punkt durchgeht und \(q_{\text{next} }\) ersetzt, sobald {{c3::\(p\) rechts von \(q, q_{\text{next} }\) liegt}}:<br><br><img src="paste-8d336e2090420fa0d8fafedb9c6d421ac7dbb985.jpg">
Extra <img src="paste-25618b2cd3adf988e817d2c4b7e2120166fa0b01.jpg">
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 34: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: |a8B?Z@Z2c
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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
ReachabilityCounting: Korrektheitsgarantie
Mit \(\ell = \lceil 2\log_2(2n/\delta)\rceil\) erfüllen die Werte \(\tilde n_v\):\[{{c1::\tfrac{n_v}{20} < \tilde n_v < 20 n_v}}\]für alle Knoten \(v\) gleichzeitig, mit Wahrscheinlichkeit \(\geq 1 - \delta\).

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten
ReachabilityCounting: Korrektheitsgarantie
Mit \(\ell = \lceil 2\log_2(2n/\delta)\rceil\) erfüllen die Werte \(\tilde n_v\):\[{{c1::\tfrac{n_v}{20} < \tilde n_v < 20 n_v}}\]für alle Knoten \(v\) gleichzeitig, mit Wahrscheinlichkeit \(\geq 1 - \delta\).
Field-by-field Comparison
Field Before After
Text <b>ReachabilityCounting: Korrektheitsgarantie</b><br>Mit \(\ell = \lceil 2\log_2(2n/\delta)\rceil\) erfüllen die Werte \(\tilde n_v\):\[{{c1::\tfrac{n_v}{20} &lt; \tilde n_v &lt; 20 n_v}}\]für <b>alle</b> Knoten \(v\) gleichzeitig, mit Wahrscheinlichkeit {{c2::\(\geq 1 - \delta\)}}.
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::6._Zählen_erreichbarer_Knoten

Note 35: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Cloze
GUID: }z)}~szKhW
modified

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Konvexe Hülle \(\operatorname{conv}(S)\).
Die konvexe Hülle einer Menge \(S \subseteq \mathbb{R}^d\) ist der Schnitt aller konvexen Mengen, die \(S\) enthalten:\[\operatorname{conv}(S) := {{c1::\bigcap_{S \subseteq C \subseteq \mathbb{R}^d,\ C \text{ konvex} } C}}.\]Äquivalent: (i) der Schnitt aller Halbebenen, die \(S\) enthalten, (ii) die kleinste konvexe Menge, die \(S\) enthält.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Konvexe Hülle \(\operatorname{conv}(S)\).
Die konvexe Hülle einer Menge \(S \subseteq \mathbb{R}^d\) ist der Schnitt aller konvexen Mengen, die \(S\) enthalten:\[\operatorname{conv}(S) := {{c1::\bigcap_{S \subseteq C \subseteq \mathbb{R}^d,\ C \text{ konvex} } C}}.\]Äquivalent: (i) der Schnitt aller Halbebenen, die \(S\) enthalten, (ii) die kleinste konvexe Menge, die \(S\) enthält.

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Konvexe Hülle \(\operatorname{conv}(S)\).
Die konvexe Hülle einer Menge \(S \subseteq \mathbb{R}^d\) ist der Schnitt aller konvexen Mengen, die \(S\) enthalten:\[\operatorname{conv}(S) := {{c1::\bigcap_{S \subseteq C \subseteq \mathbb{R}^d,\ C \text{ konvex} } C}}.\]Äquivalent:
  1. der Schnitt aller Halbebenen, die \(S\) enthalten
  2. die kleinste konvexe Menge, die \(S\) enthält

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ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle
Konvexe Hülle \(\operatorname{conv}(S)\).
Die konvexe Hülle einer Menge \(S \subseteq \mathbb{R}^d\) ist der Schnitt aller konvexen Mengen, die \(S\) enthalten:\[\operatorname{conv}(S) := {{c1::\bigcap_{S \subseteq C \subseteq \mathbb{R}^d,\ C \text{ konvex} } C}}.\]Äquivalent:
  1. der Schnitt aller Halbebenen, die \(S\) enthalten
  2. die kleinste konvexe Menge, die \(S\) enthält
Field-by-field Comparison
Field Before After
Text <b>Konvexe Hülle \(\operatorname{conv}(S)\).</b><br>Die konvexe Hülle einer Menge \(S \subseteq \mathbb{R}^d\) ist {{c1::der Schnitt aller konvexen Mengen, die \(S\) enthalten}}:\[\operatorname{conv}(S) := {{c1::\bigcap_{S \subseteq C \subseteq \mathbb{R}^d,\ C \text{ konvex} } C}}.\]Äquivalent: (i) {{c2::der Schnitt aller Halbebenen, die \(S\) enthalten}}, (ii) {{c3::die kleinste konvexe Menge, die \(S\) enthält}}. <b>Konvexe Hülle \(\operatorname{conv}(S)\).</b><br>Die konvexe Hülle einer Menge \(S \subseteq \mathbb{R}^d\) ist {{c1::der Schnitt aller konvexen Mengen, die \(S\) enthalten}}:\[\operatorname{conv}(S) := {{c1::\bigcap_{S \subseteq C \subseteq \mathbb{R}^d,\ C \text{ konvex} } C}}.\]Äquivalent:<br><ol><li>{{c2::der Schnitt aller Halbebenen, die \(S\) enthalten}}</li><li>{{c3::die kleinste konvexe Menge, die \(S\) enthält}}</li></ol>
Tags: ETH::2._Semester::A&W::3._Algorithmen_-_Highlights::1._Graphenalgorithmen::5._Konvexe_Hülle

Note 36: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::7._Integralrechnung::3._Rechenregeln::4._Substitution ETH::2._Semester::Analysis::Serie::12
Seien \(a < b\), \(f : \mathbb{R} \to \mathbb{R}\) stetig und \(g : \mathbb{R} \to \mathbb{R}\) stetig differenzierbar. Welche Formel ist richtig?
  1. \(\int_{g(a)}^{g(b)} f(g(x)) g'(x)\,dx = \int_a^b f(t)\,dt\).
  2. \(\int_a^b f(g(x)) g'(x)\,dx = \int_{g(a)}^{g(b)} f(t)\,dt\).
  3. \(\int_a^b f(g(x))\,dx = \int_{g(a)}^{g(b)} f(t) g'(t)\,dt\).
  4. \(\int_a^b f(g(x)) g'(x)\,dx = \int_{f(a)}^{f(b)} f(t)\,dt\).

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ETH::2._Semester::Analysis::7._Integralrechnung::3._Rechenregeln::4._Substitution ETH::2._Semester::Analysis::Serie::12
Seien \(a < b\), \(f : \mathbb{R} \to \mathbb{R}\) stetig und \(g : \mathbb{R} \to \mathbb{R}\) stetig differenzierbar. Welche Formel ist richtig?
  1. \(\int_{g(a)}^{g(b)} f(g(x)) g'(x)\,dx = \int_a^b f(t)\,dt\).
  2. \(\int_a^b f(g(x)) g'(x)\,dx = \int_{g(a)}^{g(b)} f(t)\,dt\).
  3. \(\int_a^b f(g(x))\,dx = \int_{g(a)}^{g(b)} f(t) g'(t)\,dt\).
  4. \(\int_a^b f(g(x)) g'(x)\,dx = \int_{f(a)}^{f(b)} f(t)\,dt\).

(b) ist richtig.

Die Substitutionsregel lautet \(\int_a^b f(g(x)) g'(x)\,dx = \int_{g(a)}^{g(b)} f(t)\,dt\) (Substitution \(t = g(x)\), \(dt = g'(x)\,dx\); die Grenzen werden mittels \(g\) transformiert).
Field-by-field Comparison
Field Before After
Front Seien \(a &lt; b\), \(f : \mathbb{R} \to \mathbb{R}\) stetig und \(g : \mathbb{R} \to \mathbb{R}\) stetig differenzierbar. Welche Formel ist richtig?<ol type="a"><li>\(\int_{g(a)}^{g(b)} f(g(x)) g'(x)\,dx = \int_a^b f(t)\,dt\).</li><li>\(\int_a^b f(g(x)) g'(x)\,dx = \int_{g(a)}^{g(b)} f(t)\,dt\).</li><li>\(\int_a^b f(g(x))\,dx = \int_{g(a)}^{g(b)} f(t) g'(t)\,dt\).</li><li>\(\int_a^b f(g(x)) g'(x)\,dx = \int_{f(a)}^{f(b)} f(t)\,dt\).</li></ol>
Back <b>(b)</b> ist richtig.<br><br>Die Substitutionsregel lautet \(\int_a^b f(g(x)) g'(x)\,dx = \int_{g(a)}^{g(b)} f(t)\,dt\) (Substitution \(t = g(x)\), \(dt = g'(x)\,dx\); die Grenzen werden mittels \(g\) transformiert).
Tags: ETH::2._Semester::Analysis::7._Integralrechnung::3._Rechenregeln::4._Substitution ETH::2._Semester::Analysis::Serie::12

Note 37: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::7._Integralrechnung::8._Hauptsatz_und_Korollare ETH::2._Semester::Analysis::Serie::12
Was ist die Ableitung nach \(x\) von \(G(x) = \int_{x^2}^{1} \sin(t)^2 \cos(t)^2\,dt\)?
  1. \(G'(x) = \int_{2x}^{1} \sin(t)^2 \cos(t)^2\,dt\).
  2. \(G'(x) = 2x \sin(x^2)^2 \cos(x^2)^2\).
  3. \(G'(x) = -\sin(x^2)^2 \cos(x^2)^2\).
  4. \(G'(x) = -2x \sin(x^2)^2 \cos(x^2)^2\).

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ETH::2._Semester::Analysis::7._Integralrechnung::8._Hauptsatz_und_Korollare ETH::2._Semester::Analysis::Serie::12
Was ist die Ableitung nach \(x\) von \(G(x) = \int_{x^2}^{1} \sin(t)^2 \cos(t)^2\,dt\)?
  1. \(G'(x) = \int_{2x}^{1} \sin(t)^2 \cos(t)^2\,dt\).
  2. \(G'(x) = 2x \sin(x^2)^2 \cos(x^2)^2\).
  3. \(G'(x) = -\sin(x^2)^2 \cos(x^2)^2\).
  4. \(G'(x) = -2x \sin(x^2)^2 \cos(x^2)^2\).

(d) \(G'(x) = -2x \sin(x^2)^2 \cos(x^2)^2\).

Mit \(h(t) = \sin(t)^2\cos(t)^2\) ist \(G(x) = \int_{x^2}^{1} h(t)\,dt = -\int_{1}^{x^2} h(t)\,dt\). Nach Hauptsatz und Kettenregel: \(G'(x) = -h(x^2) \cdot (x^2)' = -2x\,h(x^2)\).
Field-by-field Comparison
Field Before After
Front Was ist die Ableitung nach \(x\) von \(G(x) = \int_{x^2}^{1} \sin(t)^2 \cos(t)^2\,dt\)?<ol type="a"><li>\(G'(x) = \int_{2x}^{1} \sin(t)^2 \cos(t)^2\,dt\).</li><li>\(G'(x) = 2x \sin(x^2)^2 \cos(x^2)^2\).</li><li>\(G'(x) = -\sin(x^2)^2 \cos(x^2)^2\).</li><li>\(G'(x) = -2x \sin(x^2)^2 \cos(x^2)^2\).</li></ol>
Back <b>(d)</b> \(G'(x) = -2x \sin(x^2)^2 \cos(x^2)^2\).<br><br>Mit \(h(t) = \sin(t)^2\cos(t)^2\) ist \(G(x) = \int_{x^2}^{1} h(t)\,dt = -\int_{1}^{x^2} h(t)\,dt\). Nach Hauptsatz und Kettenregel: \(G'(x) = -h(x^2) \cdot (x^2)' = -2x\,h(x^2)\).
Tags: ETH::2._Semester::Analysis::7._Integralrechnung::8._Hauptsatz_und_Korollare ETH::2._Semester::Analysis::Serie::12

Note 38: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::7._Integralrechnung::4._Eigenschaften_bestimmtes_Integral ETH::2._Semester::Analysis::Serie::12
Welchen Wert hat das Integral \(\int_{-2}^{2} \left(1 + |x|\right)\,dx\)?
  1. \(0\).
  2. \(5\).
  3. \(-7\).
  4. \(8\).

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ETH::2._Semester::Analysis::7._Integralrechnung::4._Eigenschaften_bestimmtes_Integral ETH::2._Semester::Analysis::Serie::12
Welchen Wert hat das Integral \(\int_{-2}^{2} \left(1 + |x|\right)\,dx\)?
  1. \(0\).
  2. \(5\).
  3. \(-7\).
  4. \(8\).

(d) Der Wert ist \(8\).

\(\int_{-2}^{2} 1\,dx = 4\) und \(\int_{-2}^{2} |x|\,dx = 2\int_{0}^{2} x\,dx = 2 \cdot 2 = 4\). Summe: \(4 + 4 = 8\).
Field-by-field Comparison
Field Before After
Front Welchen Wert hat das Integral \(\int_{-2}^{2} \left(1 + |x|\right)\,dx\)?<ol type="a"><li>\(0\).</li><li>\(5\).</li><li>\(-7\).</li><li>\(8\).</li></ol>
Back <b>(d)</b> Der Wert ist \(8\).<br><br>\(\int_{-2}^{2} 1\,dx = 4\) und \(\int_{-2}^{2} |x|\,dx = 2\int_{0}^{2} x\,dx = 2 \cdot 2 = 4\). Summe: \(4 + 4 = 8\).<br>
Tags: ETH::2._Semester::Analysis::7._Integralrechnung::4._Eigenschaften_bestimmtes_Integral ETH::2._Semester::Analysis::Serie::12

Note 39: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::7._Integralrechnung::7._Mittelwertsatz ETH::2._Semester::Analysis::Serie::12
Ist die folgende Aussage wahr?

Sei \(f : [a,b] \to \mathbb{R}\) eine Funktion.
Dann gibt es \(c \in [a,b]\) mit \(\int_a^b f(x)\,dx = f(c)(b-a)\).
  1. Ja.
  2. Nein.

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ETH::2._Semester::Analysis::7._Integralrechnung::7._Mittelwertsatz ETH::2._Semester::Analysis::Serie::12
Ist die folgende Aussage wahr?

Sei \(f : [a,b] \to \mathbb{R}\) eine Funktion.
Dann gibt es \(c \in [a,b]\) mit \(\int_a^b f(x)\,dx = f(c)(b-a)\).
  1. Ja.
  2. Nein.

(b) Nein.

Der Mittelwertsatz der Integralrechnung verlangt, dass \(f\) stetig ist; ohne diese Voraussetzung ist die Aussage falsch.

Gegenbeispiel auf \([0,1]\):
\(f(x) = 0\) für \(x \in [0, \tfrac{1}{2})\) und \(f(x) = 1\) für \(x \in [\tfrac{1}{2}, 1]\).
Dann ist \(\int_0^1 f(x)\,dx = \tfrac{1}{2}\), aber \(f\) nimmt den Wert \(\tfrac{1}{2}\) nie an, es gibt also kein \(c\) mit \(f(c) = \tfrac{1}{2}\).
Field-by-field Comparison
Field Before After
Front Ist die folgende Aussage wahr? <br><br>Sei \(f : [a,b] \to \mathbb{R}\) eine Funktion. <br>Dann gibt es \(c \in [a,b]\) mit \(\int_a^b f(x)\,dx = f(c)(b-a)\).<ol type="a"><li>Ja.</li><li>Nein.</li></ol>
Back <b>(b)</b> Nein.<br><br>Der Mittelwertsatz der Integralrechnung verlangt, dass \(f\) <b>stetig</b> ist; ohne diese Voraussetzung ist die Aussage falsch. <br><br>Gegenbeispiel auf \([0,1]\): <br>\(f(x) = 0\) für \(x \in [0, \tfrac{1}{2})\) und \(f(x) = 1\) für \(x \in [\tfrac{1}{2}, 1]\). <br>Dann ist \(\int_0^1 f(x)\,dx = \tfrac{1}{2}\), aber \(f\) nimmt den Wert \(\tfrac{1}{2}\) nie an, es gibt also kein \(c\) mit \(f(c) = \tfrac{1}{2}\).
Tags: ETH::2._Semester::Analysis::7._Integralrechnung::7._Mittelwertsatz ETH::2._Semester::Analysis::Serie::12

Note 40: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::7._Integralrechnung::5._Integrierbarkeitskriterien ETH::2._Semester::Analysis::Serie::12
Welche der folgenden Implikationsketten ist richtig (auf einem kompakten Intervall)?
  1. \(f\) differenzierbar \(\Rightarrow\) \(f\) stetig \(\Rightarrow\) \(f\) integrierbar.
  2. \(f\) integrierbar \(\Rightarrow\) \(f\) differenzierbar \(\Rightarrow\) \(f\) stetig.
  3. \(f\) stetig \(\Rightarrow\) \(f\) differenzierbar \(\Rightarrow\) \(f\) integrierbar.
  4. \(f\) integrierbar \(\Rightarrow\) \(f\) stetig \(\Rightarrow\) \(f\) differenzierbar.
  5. keine.

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ETH::2._Semester::Analysis::7._Integralrechnung::5._Integrierbarkeitskriterien ETH::2._Semester::Analysis::Serie::12
Welche der folgenden Implikationsketten ist richtig (auf einem kompakten Intervall)?
  1. \(f\) differenzierbar \(\Rightarrow\) \(f\) stetig \(\Rightarrow\) \(f\) integrierbar.
  2. \(f\) integrierbar \(\Rightarrow\) \(f\) differenzierbar \(\Rightarrow\) \(f\) stetig.
  3. \(f\) stetig \(\Rightarrow\) \(f\) differenzierbar \(\Rightarrow\) \(f\) integrierbar.
  4. \(f\) integrierbar \(\Rightarrow\) \(f\) stetig \(\Rightarrow\) \(f\) differenzierbar.
  5. keine.

(a) ist richtig.

Differenzierbarkeit impliziert Stetigkeit, und jede stetige Funktion auf einem kompakten Intervall ist (Riemann-)integrierbar. Die Umkehrungen gelten nicht, daher sind (b), (c) und (d) falsch.
Field-by-field Comparison
Field Before After
Front Welche der folgenden Implikationsketten ist richtig (auf einem kompakten Intervall)?<ol type="a"><li>\(f\) differenzierbar \(\Rightarrow\) \(f\) stetig \(\Rightarrow\) \(f\) integrierbar.</li><li>\(f\) integrierbar \(\Rightarrow\) \(f\) differenzierbar \(\Rightarrow\) \(f\) stetig.</li><li>\(f\) stetig \(\Rightarrow\) \(f\) differenzierbar \(\Rightarrow\) \(f\) integrierbar.</li><li>\(f\) integrierbar \(\Rightarrow\) \(f\) stetig \(\Rightarrow\) \(f\) differenzierbar.</li><li>keine.</li></ol>
Back <b>(a)</b> ist richtig.<br><br>Differenzierbarkeit impliziert Stetigkeit, und jede stetige Funktion auf einem kompakten Intervall ist (Riemann-)integrierbar. Die Umkehrungen gelten nicht, daher sind (b), (c) und (d) falsch.
Tags: ETH::2._Semester::Analysis::7._Integralrechnung::5._Integrierbarkeitskriterien ETH::2._Semester::Analysis::Serie::12

Note 41: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution
Substitution bei in den Variablen homogenen DGl
Eine DGl der Form \(y' = g\!\left(\dfrac{y}{x}\right)\) heisst homogen in den Variablen und lässt sich durch die Substitution
\[ {{c2::u = \frac{y}{x} }} \]in eine DGl mit trennbaren Variablen überführen.

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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution
Substitution bei in den Variablen homogenen DGl
Eine DGl der Form \(y' = g\!\left(\dfrac{y}{x}\right)\) heisst homogen in den Variablen und lässt sich durch die Substitution
\[ {{c2::u = \frac{y}{x} }} \]in eine DGl mit trennbaren Variablen überführen.

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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution
Eine DGl der Form \(y' = g\!\left(\dfrac{y}{x}\right)\) heisst homogen in den Variablen und lässt sich durch die Substitution
\[ {{c2::u = \frac{y}{x} }} \]in eine DGl mit trennbaren Variablen überführen.

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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution
Eine DGl der Form \(y' = g\!\left(\dfrac{y}{x}\right)\) heisst homogen in den Variablen und lässt sich durch die Substitution
\[ {{c2::u = \frac{y}{x} }} \]in eine DGl mit trennbaren Variablen überführen.
Field-by-field Comparison
Field Before After
Text <b>Substitution bei in den Variablen homogenen DGl</b><br>Eine DGl der Form&nbsp;\(y' = g\!\left(\dfrac{y}{x}\right)\)&nbsp;heisst {{c1::homogen in den Variablen}} und lässt sich durch die Substitution<br>\[ {{c2::u = \frac{y}{x} }} \]in eine DGl mit {{c3::trennbaren Variablen}} überführen. Eine DGl der Form&nbsp;\(y' = g\!\left(\dfrac{y}{x}\right)\)&nbsp;heisst {{c1::homogen in den Variablen}} und lässt sich durch die Substitution<br>\[ {{c2::u = \frac{y}{x} }} \]in eine DGl mit {{c3::trennbaren Variablen}} überführen.
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution

Note 42: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::7._Integralrechnung::5._Integrierbarkeitskriterien ETH::2._Semester::Analysis::Serie::12
Welche Eigenschaft einer Funktion auf einem kompakten Intervall impliziert nicht die Integrierbarkeit?
  1. Beschränktheit.
  2. Monotonie.
  3. Stetigkeit.
  4. Differenzierbarkeit.

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ETH::2._Semester::Analysis::7._Integralrechnung::5._Integrierbarkeitskriterien ETH::2._Semester::Analysis::Serie::12
Welche Eigenschaft einer Funktion auf einem kompakten Intervall impliziert nicht die Integrierbarkeit?
  1. Beschränktheit.
  2. Monotonie.
  3. Stetigkeit.
  4. Differenzierbarkeit.

(a) Beschränktheit allein genügt nicht.

Gegenbeispiel: die Dirichlet-Funktion (\(1\) auf den Rationalen, \(0\) sonst) ist beschränkt, aber nicht Riemann-integrierbar. Monotonie, Stetigkeit und Differenzierbarkeit implizieren jeweils Integrierbarkeit.
Field-by-field Comparison
Field Before After
Front Welche Eigenschaft einer Funktion auf einem kompakten Intervall impliziert <b>nicht</b> die Integrierbarkeit?<ol type="a"><li>Beschränktheit.</li><li>Monotonie.</li><li>Stetigkeit.</li><li>Differenzierbarkeit.</li></ol>
Back <b>(a)</b> Beschränktheit allein genügt nicht.<br><br>Gegenbeispiel: die Dirichlet-Funktion (\(1\) auf den Rationalen, \(0\) sonst) ist beschränkt, aber nicht Riemann-integrierbar. Monotonie, Stetigkeit und Differenzierbarkeit implizieren jeweils Integrierbarkeit.
Tags: ETH::2._Semester::Analysis::7._Integralrechnung::5._Integrierbarkeitskriterien ETH::2._Semester::Analysis::Serie::12

Note 43: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::5._Differentialrechnung::6._Mittelwertsätze ETH::2._Semester::Analysis::Serie::10
Seien \(F_1, F_2 : (a, b) \rightarrow \mathbb{R}\) zwei differenzierbare Funktionen, deren Ableitungen gleich sind: \(F_1\'(x) = F_2\'(x)\) für alle \(x \in (a, b)\). Dann gilt \(F_1(x) = F_2(x)\) für alle \(x \in (a, b)\).
  1. Richtig.
  2. Falsch.

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ETH::2._Semester::Analysis::5._Differentialrechnung::6._Mittelwertsätze ETH::2._Semester::Analysis::Serie::10
Seien \(F_1, F_2 : (a, b) \rightarrow \mathbb{R}\) zwei differenzierbare Funktionen, deren Ableitungen gleich sind: \(F_1\'(x) = F_2\'(x)\) für alle \(x \in (a, b)\). Dann gilt \(F_1(x) = F_2(x)\) für alle \(x \in (a, b)\).
  1. Richtig.
  2. Falsch.

(b) Falsch. Zwei Funktionen mit gleicher Ableitung können sich um eine additive Konstante unterscheiden, z.B. \(F_1(x) = x\) und \(F_2(x) = x + 1\).

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ETH::2._Semester::Analysis::5._Differentialrechnung::6._Mittelwertsätze ETH::2._Semester::Analysis::Serie::10
Seien \(F_1, F_2 : (a, b) \rightarrow \mathbb{R}\) zwei differenzierbare Funktionen, deren Ableitungen gleich sind: \(F_1'(x) = F_2'(x)\) für alle \(x \in (a, b)\). Dann gilt \(F_1(x) = F_2(x)\) für alle \(x \in (a, b)\).
  1. Richtig.
  2. Falsch.

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ETH::2._Semester::Analysis::5._Differentialrechnung::6._Mittelwertsätze ETH::2._Semester::Analysis::Serie::10
Seien \(F_1, F_2 : (a, b) \rightarrow \mathbb{R}\) zwei differenzierbare Funktionen, deren Ableitungen gleich sind: \(F_1'(x) = F_2'(x)\) für alle \(x \in (a, b)\). Dann gilt \(F_1(x) = F_2(x)\) für alle \(x \in (a, b)\).
  1. Richtig.
  2. Falsch.

(b) Falsch. Zwei Funktionen mit gleicher Ableitung können sich um eine additive Konstante unterscheiden, z.B. \(F_1(x) = x\) und \(F_2(x) = x + 1\).
Field-by-field Comparison
Field Before After
Front Seien \(F_1, F_2 : (a, b) \rightarrow \mathbb{R}\) zwei differenzierbare Funktionen, deren Ableitungen gleich sind: \(F_1\'(x) = F_2\'(x)\) für alle \(x \in (a, b)\). Dann gilt \(F_1(x) = F_2(x)\) für alle \(x \in (a, b)\).<ol type="a"><li>Richtig.</li><li>Falsch.</li></ol> Seien \(F_1, F_2 : (a, b) \rightarrow \mathbb{R}\) zwei differenzierbare Funktionen, deren Ableitungen gleich sind: \(F_1'(x) = F_2'(x)\) für alle \(x \in (a, b)\). Dann gilt \(F_1(x) = F_2(x)\) für alle \(x \in (a, b)\).<ol type="a"><li>Richtig.</li><li>Falsch.</li></ol>
Tags: ETH::2._Semester::Analysis::5._Differentialrechnung::6._Mittelwertsätze ETH::2._Semester::Analysis::Serie::10

Note 44: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer polynomialen Störfunktion
Störfunktion \(s(t) = a_0 + a_1 t + \dots + a_n t^n\):
\[ y(t) = C_0 + C_1 t + \dots + C_n t^n \]Spezialfall (Resonanz): Ist \(0\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = (C_0 + C_1 t + \dots + C_n t^n)\, t^m \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer polynomialen Störfunktion
Störfunktion \(s(t) = a_0 + a_1 t + \dots + a_n t^n\):
\[ y(t) = C_0 + C_1 t + \dots + C_n t^n \]Spezialfall (Resonanz): Ist \(0\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = (C_0 + C_1 t + \dots + C_n t^n)\, t^m \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer polynomialen Störfunktion
Störfunktion \(s(t) = a_0 + a_1 t + \dots + a_n t^n\):
\[ y(t) = C_0 + C_1 t + \dots + C_n t^n \]Spezialfall (Resonanz): Ist \(0\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = (C_0 + C_1 t + \dots + C_n t^n)\, t^m \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer polynomialen Störfunktion
Störfunktion \(s(t) = a_0 + a_1 t + \dots + a_n t^n\):
\[ y(t) = C_0 + C_1 t + \dots + C_n t^n \]Spezialfall (Resonanz): Ist \(0\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = (C_0 + C_1 t + \dots + C_n t^n)\, t^m \]
Field-by-field Comparison
Field Before After
Text <b>Ansatz für die partikuläre Lösung</b> bei einer <b>polynomialen</b> Störfunktion<br>Störfunktion&nbsp;\(s(t) = a_0 + a_1 t + \dots + a_n t^n\):<br>\[ y(t) = {{c1::C_0 + C_1 t + \dots + C_n t^n}} \]<b>Spezialfall</b> (Resonanz): Ist&nbsp;\(0\)&nbsp;eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz<br>\[ y(t) = {{c2::(C_0 + C_1 t + \dots + C_n t^n)\, t^m}} \] <b>Ansatz für die partikuläre Lösung</b> bei einer <b>polynomialen</b> Störfunktion<br>Störfunktion&nbsp;\(s(t) = {{c1::a_0 + a_1 t + \dots + a_n t^n}}\):<br>\[ y(t) = {{c1::C_0 + C_1 t + \dots + C_n t^n}} \]<b>Spezialfall</b> (Resonanz): Ist&nbsp;\(0\)&nbsp;eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz<br>\[ y(t) = {{c1::(C_0 + C_1 t + \dots + C_n t^n)\, t^m}} \]
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung

Note 45: ETH::2. Semester::Analysis

Deck: ETH::2. Semester::Analysis
Note Type: Horvath Cloze
GUID: 82eDk`nW|[
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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution
Lineare Substitution
Eine DGl der Form \(y' = f(ax + by + c)\) mit \(a, b, c \in \mathbb{R}\) lässt sich durch die Substitution
\[ u = ax + by + c \]in eine DGl mit trennbaren Variablen überführen.

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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution
Lineare Substitution
Eine DGl der Form \(y' = f(ax + by + c)\) mit \(a, b, c \in \mathbb{R}\) lässt sich durch die Substitution
\[ u = ax + by + c \]in eine DGl mit trennbaren Variablen überführen.

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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution
Lineare Substitution
Eine DGl der Form \(y' = f(ax + by + c)\) mit \(a, b, c \in \mathbb{R}\) lässt sich durch die Substitution
\[ u = ax + by + c \]in eine DGl mit trennbaren Variablen überführen.

Back

ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution
Lineare Substitution
Eine DGl der Form \(y' = f(ax + by + c)\) mit \(a, b, c \in \mathbb{R}\) lässt sich durch die Substitution
\[ u = ax + by + c \]in eine DGl mit trennbaren Variablen überführen.
Field-by-field Comparison
Field Before After
Text <b>Lineare Substitution</b><br>Eine DGl der Form&nbsp;\(y' = f(ax + by + c)\)&nbsp;mit&nbsp;\(a, b, c \in \mathbb{R}\)&nbsp;lässt sich durch die Substitution<br>\[ {{c1::u = ax + by + c}} \]in eine DGl mit {{c2::trennbaren Variablen}} überführen. <b>Lineare Substitution</b><br>Eine DGl der Form&nbsp;\(y' = f(ax + by + c)\)&nbsp;mit&nbsp;\(a, b, c \in \mathbb{R}\)&nbsp;lässt sich durch die Substitution<br>\[ {{c1::u = ax + by + c}} \]in eine DGl mit trennbaren Variablen überführen.
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution

Note 46: ETH::2. Semester::Analysis

Deck: ETH::2. Semester::Analysis
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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::1._Trennung_der_Variablen ETH::2._Semester::Analysis::Serie::13
Welche der folgenden Differentialgleichungen können durch Trennung der Variablen gelöst werden? (Mehrfachauswahl möglich.)
  1. \(y' = y\).
  2. \(y' = xy\).
  3. \(y' = \ln(xy)\).
  4. \(y' = \sin(x)\cos(xy)\).
  5. \(y' = 2x\).
  6. \(y' = x + y\).
  7. \(y' = \sin(x+y)\).
  8. \(y' = y/x\).
  9. \(y' = \sin(x)\cos(y)\).
  10. \(y' = e^{x+y}\).
  11. \(y' = \dfrac{x+y}{x+2y}\).

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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::1._Trennung_der_Variablen ETH::2._Semester::Analysis::Serie::13
Welche der folgenden Differentialgleichungen können durch Trennung der Variablen gelöst werden? (Mehrfachauswahl möglich.)
  1. \(y' = y\).
  2. \(y' = xy\).
  3. \(y' = \ln(xy)\).
  4. \(y' = \sin(x)\cos(xy)\).
  5. \(y' = 2x\).
  6. \(y' = x + y\).
  7. \(y' = \sin(x+y)\).
  8. \(y' = y/x\).
  9. \(y' = \sin(x)\cos(y)\).
  10. \(y' = e^{x+y}\).
  11. \(y' = \dfrac{x+y}{x+2y}\).

Richtig: (a), (b), (e), (h), (i), (j).

Trennbar heisst, die rechte Seite lässt sich als Produkt \(g(x)\,h(y)\) schreiben:
(a) \(y' = 1 \cdot y\); (b) \(y' = x \cdot y\); (e) \(y' = 2x \cdot 1\); (h) \(y' = \tfrac{1}{x}\cdot y\); (i) \(y' = \sin(x)\cos(y)\); (j) \(y' = e^x e^y\).

Nicht trennbar: (c), (d), (f), (g), (k), da sich \(x\) und \(y\) nicht in ein Produkt separater Faktoren zerlegen lassen (z.B. \(\ln(xy)\), \(\cos(xy)\), \(\sin(x+y)\), \(x+y\) sind nicht faktorisierbar).
Field-by-field Comparison
Field Before After
Front Welche der folgenden Differentialgleichungen können durch Trennung der Variablen gelöst werden? (Mehrfachauswahl möglich.)<ol type="a"><li>\(y' = y\).</li><li>\(y' = xy\).</li><li>\(y' = \ln(xy)\).</li><li>\(y' = \sin(x)\cos(xy)\).</li><li>\(y' = 2x\).</li><li>\(y' = x + y\).</li><li>\(y' = \sin(x+y)\).</li><li>\(y' = y/x\).</li><li>\(y' = \sin(x)\cos(y)\).</li><li>\(y' = e^{x+y}\).</li><li>\(y' = \dfrac{x+y}{x+2y}\).</li></ol>
Back Richtig: <b>(a)</b>, <b>(b)</b>, <b>(e)</b>, <b>(h)</b>, <b>(i)</b>, <b>(j)</b>.<br><br>Trennbar heisst, die rechte Seite lässt sich als Produkt \(g(x)\,h(y)\) schreiben:<br>(a) \(y' = 1 \cdot y\); (b) \(y' = x \cdot y\); (e) \(y' = 2x \cdot 1\); (h) \(y' = \tfrac{1}{x}\cdot y\); (i) \(y' = \sin(x)\cos(y)\); (j) \(y' = e^x e^y\).<br><br>Nicht trennbar: (c), (d), (f), (g), (k), da sich \(x\) und \(y\) nicht in ein Produkt separater Faktoren zerlegen lassen (z.B. \(\ln(xy)\), \(\cos(xy)\), \(\sin(x+y)\), \(x+y\) sind nicht faktorisierbar).
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::1._Trennung_der_Variablen ETH::2._Semester::Analysis::Serie::13

Note 47: ETH::2. Semester::Analysis

Deck: ETH::2. Semester::Analysis
Note Type: Horvath Cloze
GUID: F.4_b[[a[X
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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer exponentiellen Störfunktion
Störfunktion \(s(t) = A e^{kt}\):
\[ y(t) = {{c1::C e^{kt} }} \]Spezialfall (Resonanz): Ist \(k\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = {{c2::(C e^{kt})\, t^m}} \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer exponentiellen Störfunktion
Störfunktion \(s(t) = A e^{kt}\):
\[ y(t) = {{c1::C e^{kt} }} \]Spezialfall (Resonanz): Ist \(k\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = {{c2::(C e^{kt})\, t^m}} \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer exponentiellen Störfunktion
Störfunktion \(s(t) = A e^{kt}\):
\[ y(t) = {{c1::C e^{kt} }} \]Spezialfall (Resonanz): Ist \(k\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = {{c1::(C e^{kt})\, t^m}} \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer exponentiellen Störfunktion
Störfunktion \(s(t) = A e^{kt}\):
\[ y(t) = {{c1::C e^{kt} }} \]Spezialfall (Resonanz): Ist \(k\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = {{c1::(C e^{kt})\, t^m}} \]
Field-by-field Comparison
Field Before After
Text <b>Ansatz für die partikuläre Lösung</b> bei einer <b>exponentiellen</b> Störfunktion<br>Störfunktion&nbsp;\(s(t) = A e^{kt}\):<br>\[ y(t) = {{c1::C e^{kt} }} \]<b>Spezialfall</b> (Resonanz): Ist&nbsp;\(k\)&nbsp;eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz<br>\[ y(t) = {{c2::(C e^{kt})\, t^m}} \] <b>Ansatz für die partikuläre Lösung</b> bei einer <b>exponentiellen</b> Störfunktion<br>Störfunktion&nbsp;\(s(t) = A e^{kt}\):<br>\[ y(t) = {{c1::C e^{kt} }} \]<b>Spezialfall</b> (Resonanz): Ist&nbsp;\(k\)&nbsp;eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz<br>\[ y(t) = {{c1::(C e^{kt})\, t^m}} \]
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung

Note 48: ETH::2. Semester::Analysis

Deck: ETH::2. Semester::Analysis
Note Type: Horvath Cloze
GUID: FVZ$*)>ic6
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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::2._Variation_der_Konstanten
Variation der Konstanten: Beispiel \(y' - y = x\)
Die homogene DGl \(y' - y = 0\) hat die allgemeine Lösung \(y_h(x) = K e^x\).
Der Ansatz für die partikuläre Lösung (Variation der Konstanten) lautet daher
\[ y_p(x) = K(x)\,e^x \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::2._Variation_der_Konstanten
Variation der Konstanten: Beispiel \(y' - y = x\)
Die homogene DGl \(y' - y = 0\) hat die allgemeine Lösung \(y_h(x) = K e^x\).
Der Ansatz für die partikuläre Lösung (Variation der Konstanten) lautet daher
\[ y_p(x) = K(x)\,e^x \]

Die Konstante \(K\) wird durch die Funktion \(K(x)\) ersetzt.

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::2._Variation_der_Konstanten
Variation der Konstanten: Beispiel \(y' - y = x\)
Die homogene DGl \(y' - y = 0\) hat die allgemeine Lösung \(y_h(x) = K e^x\).
Der Ansatz für die partikuläre Lösung (Variation der Konstanten) lautet daher
\[ y_p(x) = K(x)\,e^x \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::2._Variation_der_Konstanten
Variation der Konstanten: Beispiel \(y' - y = x\)
Die homogene DGl \(y' - y = 0\) hat die allgemeine Lösung \(y_h(x) = K e^x\).
Der Ansatz für die partikuläre Lösung (Variation der Konstanten) lautet daher
\[ y_p(x) = K(x)\,e^x \]

Die Konstante \(K\) wird durch die Funktion \(K(x)\) ersetzt.
Field-by-field Comparison
Field Before After
Text <b>Variation der Konstanten: Beispiel</b>&nbsp;\(y' - y = x\)<br>Die homogene DGl&nbsp;\(y' - y = 0\)&nbsp;hat die allgemeine Lösung&nbsp;\(y_h(x) = {{c1::K e^x}}\).<br>Der Ansatz für die partikuläre Lösung (Variation der Konstanten) lautet daher<br>\[ y_p(x) = {{c2::K(x)\,e^x}} \] <b>Variation der Konstanten: Beispiel</b>&nbsp;\(y' - y = x\)<br>Die homogene DGl&nbsp;\(y' - y = 0\)&nbsp;hat die allgemeine Lösung&nbsp;\(y_h(x) = {{c1::K e^x}}\).<br>Der Ansatz für die partikuläre Lösung (Variation der Konstanten) lautet daher<br>\[ y_p(x) = {{c1::K(x)\,e^x}} \]
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::2._Variation_der_Konstanten

Note 49: ETH::2. Semester::Analysis

Deck: ETH::2. Semester::Analysis
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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Wahl des Ansatzes für die partikuläre Lösung (nach Typ der Störfunktion):
  • Störfunktion ist ein Polynom \(n\)-ten Grades \(\Rightarrow\) Ansatz: ein Polynom vom gleichen Grad
  • Störfunktion ist eine Schwingung \(\Rightarrow\) Ansatz: eine Schwingung der gleichen Frequenz
  • Störfunktion ist ein Produkt aus Polynom und Exponentialfunktion \(\Rightarrow\) Ansatz: ein Produkt aus einem Polynom gleichen Grades und einer Exponentialfunktion mit gleichem Exponenten

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Wahl des Ansatzes für die partikuläre Lösung (nach Typ der Störfunktion):
  • Störfunktion ist ein Polynom \(n\)-ten Grades \(\Rightarrow\) Ansatz: ein Polynom vom gleichen Grad
  • Störfunktion ist eine Schwingung \(\Rightarrow\) Ansatz: eine Schwingung der gleichen Frequenz
  • Störfunktion ist ein Produkt aus Polynom und Exponentialfunktion \(\Rightarrow\) Ansatz: ein Produkt aus einem Polynom gleichen Grades und einer Exponentialfunktion mit gleichem Exponenten

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Wahl des Ansatzes für die partikuläre Lösung (nach Typ der Störfunktion):
  • Störfunktion ist ein Polynom \(n\)-ten Grades \(\Rightarrow\) Ansatz: ein Polynom vom gleichen Grad
  • Störfunktion ist eine Schwingung \(\Rightarrow\) Ansatz: eine Schwingung der gleichen Frequenz
  • Störfunktion ist ein Produkt aus Polynom und Exponentialfunktion \(\Rightarrow\) Ansatz: ein Produkt aus einem Polynom gleichen Grades und einer Exponentialfunktion mit gleichem Exponenten

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Wahl des Ansatzes für die partikuläre Lösung (nach Typ der Störfunktion):
  • Störfunktion ist ein Polynom \(n\)-ten Grades \(\Rightarrow\) Ansatz: ein Polynom vom gleichen Grad
  • Störfunktion ist eine Schwingung \(\Rightarrow\) Ansatz: eine Schwingung der gleichen Frequenz
  • Störfunktion ist ein Produkt aus Polynom und Exponentialfunktion \(\Rightarrow\) Ansatz: ein Produkt aus einem Polynom gleichen Grades und einer Exponentialfunktion mit gleichem Exponenten
Field-by-field Comparison
Field Before After
Text <b>Wahl des Ansatzes für die partikuläre Lösung</b> (nach Typ der Störfunktion):<ul><li>Störfunktion ist ein <b>Polynom</b> \(n\)-ten Grades&nbsp;\(\Rightarrow\)&nbsp;Ansatz: {{c1::ein Polynom vom gleichen Grad}}</li><li>Störfunktion ist eine <b>Schwingung</b>&nbsp;\(\Rightarrow\)&nbsp;Ansatz: {{c2::eine Schwingung der gleichen Frequenz}}</li><li>Störfunktion ist ein <b>Produkt aus Polynom und Exponentialfunktion</b>&nbsp;\(\Rightarrow\)&nbsp;Ansatz: {{c3::ein Produkt aus einem Polynom gleichen Grades und einer Exponentialfunktion mit gleichem Exponenten}}</li></ul> <b>Wahl des Ansatzes für die partikuläre Lösung</b> (nach Typ der Störfunktion):<ul><li>Störfunktion ist ein <b>Polynom</b> \(n\)-ten Grades&nbsp;\(\Rightarrow\)&nbsp;Ansatz: {{c1::ein Polynom vom gleichen Grad}}</li><li>Störfunktion ist eine <b>Schwingung</b>&nbsp;\(\Rightarrow\)&nbsp;Ansatz: {{c1::eine Schwingung der gleichen Frequenz}}</li><li>Störfunktion ist ein <b>Produkt aus Polynom und Exponentialfunktion</b>&nbsp;\(\Rightarrow\)&nbsp;Ansatz: {{c1::ein Produkt aus einem Polynom gleichen Grades und einer Exponentialfunktion mit gleichem Exponenten}}</li></ul>
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung

Note 50: ETH::2. Semester::Analysis

Deck: ETH::2. Semester::Analysis
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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::1._Lösungsstruktur ETH::2._Semester::Analysis::Serie::13
Betrachten Sie die Differentialgleichung \(2u''(x) - 8u(x) = -6e^x\). Welche der folgenden Funktionen sind Lösungen? (Mehrfachauswahl möglich.)
  1. \(5e^{-2x}\).
  2. \(3e^{2x} + e^x\).
  3. \(3e^x\).
  4. \(e^x\).

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::1._Lösungsstruktur ETH::2._Semester::Analysis::Serie::13
Betrachten Sie die Differentialgleichung \(2u''(x) - 8u(x) = -6e^x\). Welche der folgenden Funktionen sind Lösungen? (Mehrfachauswahl möglich.)
  1. \(5e^{-2x}\).
  2. \(3e^{2x} + e^x\).
  3. \(3e^x\).
  4. \(e^x\).

Richtig: (b) und (d).

Die homogene Gleichung \(2u'' - 8u = 0\) hat die Lösungen \(e^{\pm 2x}\); eine partikuläre Lösung ist \(u_p = e^x\) (denn \(2e^x - 8e^x = -6e^x\)). Allgemeine Lösung: \(u = e^x + c_1 e^{2x} + c_2 e^{-2x}\).

(d) \(e^x\): partikuläre Lösung, \(2e^x - 8e^x = -6e^x\). Richtig.
(b) \(3e^{2x} + e^x\): partikuläre plus homogene Lösung, \(2(12e^{2x} + e^x) - 8(3e^{2x} + e^x) = 24e^{2x} + 2e^x - 24e^{2x} - 8e^x = -6e^x\). Richtig.
(a) \(5e^{-2x}\): rein homogen, ergibt \(0 \neq -6e^x\). Falsch.
(c) \(3e^x\): ergibt \(6e^x - 24e^x = -18e^x \neq -6e^x\). Falsch.
Field-by-field Comparison
Field Before After
Front Betrachten Sie die Differentialgleichung \(2u''(x) - 8u(x) = -6e^x\). Welche der folgenden Funktionen sind Lösungen? (Mehrfachauswahl möglich.)<ol type="a"><li>\(5e^{-2x}\).</li><li>\(3e^{2x} + e^x\).</li><li>\(3e^x\).</li><li>\(e^x\).</li></ol>
Back Richtig: <b>(b)</b> und <b>(d)</b>.<br><br>Die homogene Gleichung \(2u'' - 8u = 0\) hat die Lösungen \(e^{\pm 2x}\); eine partikuläre Lösung ist \(u_p = e^x\) (denn \(2e^x - 8e^x = -6e^x\)). Allgemeine Lösung: \(u = e^x + c_1 e^{2x} + c_2 e^{-2x}\).<br><br>(d) \(e^x\): partikuläre Lösung, \(2e^x - 8e^x = -6e^x\). Richtig.<br>(b) \(3e^{2x} + e^x\): partikuläre plus homogene Lösung, \(2(12e^{2x} + e^x) - 8(3e^{2x} + e^x) = 24e^{2x} + 2e^x - 24e^{2x} - 8e^x = -6e^x\). Richtig.<br>(a) \(5e^{-2x}\): rein homogen, ergibt \(0 \neq -6e^x\). Falsch.<br>(c) \(3e^x\): ergibt \(6e^x - 24e^x = -18e^x \neq -6e^x\). Falsch.
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::1._Lösungsstruktur ETH::2._Semester::Analysis::Serie::13

Note 51: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::7._Integralrechnung::4._Eigenschaften_bestimmtes_Integral ETH::2._Semester::Analysis::Serie::12
In den folgenden Aussagen sind alle Funktionen beschränkt und integrierbar. Welche Aussagen sind richtig?
  1. Für \(f : [a,b] \to \mathbb{R}_{\leq 0}\) gilt \(\int_a^b f(x)\,dx \leq 0\).
  2. \(\int_a^b f(x)\,dx = 0\) impliziert \(f(x) = 0\) für alle \(x \in [a,b]\).
  3. \(\left| \int_a^b f(x)\,dx \right| \leq \sqrt{b-a}\,\sqrt{\int_a^b f(x)^2\,dx}\).
  4. Für \(F(x) = \int_a^x f(t)\,dt\) gilt \(F'(x) = f(x) + C\) für alle \(x \in [a,b]\) und \(C \in \mathbb{R}\).

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ETH::2._Semester::Analysis::7._Integralrechnung::4._Eigenschaften_bestimmtes_Integral ETH::2._Semester::Analysis::Serie::12
In den folgenden Aussagen sind alle Funktionen beschränkt und integrierbar. Welche Aussagen sind richtig?
  1. Für \(f : [a,b] \to \mathbb{R}_{\leq 0}\) gilt \(\int_a^b f(x)\,dx \leq 0\).
  2. \(\int_a^b f(x)\,dx = 0\) impliziert \(f(x) = 0\) für alle \(x \in [a,b]\).
  3. \(\left| \int_a^b f(x)\,dx \right| \leq \sqrt{b-a}\,\sqrt{\int_a^b f(x)^2\,dx}\).
  4. Für \(F(x) = \int_a^x f(t)\,dt\) gilt \(F'(x) = f(x) + C\) für alle \(x \in [a,b]\) und \(C \in \mathbb{R}\).

(a) und (c) sind richtig.

(a) Eine nichtpositive Funktion hat ein nichtpositives Integral (Monotonie des Integrals). Richtig.
(c) Cauchy-Schwarz-Ungleichung, angewendet auf \(f\) und die konstante Funktion \(1\): \(\left|\int_a^b f \cdot 1\right| \leq \sqrt{\int_a^b f^2}\,\sqrt{\int_a^b 1^2} = \sqrt{b-a}\,\sqrt{\int_a^b f^2}\). Richtig.
(b) Falsch: z.B. \(\int_{-1}^{1} x\,dx = 0\), obwohl \(f \neq 0\).
(d) Falsch: Nach dem Hauptsatz gilt \(F'(x) = f(x)\) (für stetiges \(f\)), ohne additive Konstante.
Field-by-field Comparison
Field Before After
Front In den folgenden Aussagen sind alle Funktionen beschränkt und integrierbar. Welche Aussagen sind richtig?<ol type="a"><li>Für \(f : [a,b] \to \mathbb{R}_{\leq 0}\) gilt \(\int_a^b f(x)\,dx \leq 0\).</li><li>\(\int_a^b f(x)\,dx = 0\) impliziert \(f(x) = 0\) für alle \(x \in [a,b]\).</li><li>\(\left| \int_a^b f(x)\,dx \right| \leq \sqrt{b-a}\,\sqrt{\int_a^b f(x)^2\,dx}\).</li><li>Für \(F(x) = \int_a^x f(t)\,dt\) gilt \(F'(x) = f(x) + C\) für alle \(x \in [a,b]\) und \(C \in \mathbb{R}\).</li></ol>
Back <b>(a)</b> und <b>(c)</b> sind richtig.<br><br>(a) Eine nichtpositive Funktion hat ein nichtpositives Integral (Monotonie des Integrals). Richtig.<br>(c) Cauchy-Schwarz-Ungleichung, angewendet auf \(f\) und die konstante Funktion \(1\): \(\left|\int_a^b f \cdot 1\right| \leq \sqrt{\int_a^b f^2}\,\sqrt{\int_a^b 1^2} = \sqrt{b-a}\,\sqrt{\int_a^b f^2}\). Richtig.<br>(b) Falsch: z.B. \(\int_{-1}^{1} x\,dx = 0\), obwohl \(f \neq 0\).<br>(d) Falsch: Nach dem Hauptsatz gilt \(F'(x) = f(x)\) (für stetiges \(f\)), ohne additive Konstante.<br>
Tags: ETH::2._Semester::Analysis::7._Integralrechnung::4._Eigenschaften_bestimmtes_Integral ETH::2._Semester::Analysis::Serie::12

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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution ETH::2._Semester::Analysis::Serie::13
Wie müssen \(A\) und \(B\) gewählt werden, damit die Funktion \(y(x) = A + B e^{x^2/2}\) das Anfangswertproblem \(y' - xy - x = 0\), \(y(0) = 1\) löst?
  1. \(A = 2,\ B = -1\).
  2. \(A = 1,\ B = 0\).
  3. \(A = -1,\ B = 1\).
  4. \(A = -1,\ B = 2\).

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ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution ETH::2._Semester::Analysis::Serie::13
Wie müssen \(A\) und \(B\) gewählt werden, damit die Funktion \(y(x) = A + B e^{x^2/2}\) das Anfangswertproblem \(y' - xy - x = 0\), \(y(0) = 1\) löst?
  1. \(A = 2,\ B = -1\).
  2. \(A = 1,\ B = 0\).
  3. \(A = -1,\ B = 1\).
  4. \(A = -1,\ B = 2\).

(d) \(A = -1,\ B = 2\).

Mit \(y = A + Be^{x^2/2}\) ist \(y' = Bx\,e^{x^2/2}\). Einsetzen in \(y' = xy + x = x(y+1)\): \(Bx\,e^{x^2/2} = x\left(A + 1 + Be^{x^2/2}\right)\). Der Term \(xBe^{x^2/2}\) hebt sich auf, es bleibt \(0 = x(A+1)\), also \(A = -1\). Die Anfangsbedingung \(y(0) = A + B = 1\) liefert \(B = 2\).
Field-by-field Comparison
Field Before After
Front Wie müssen \(A\) und \(B\) gewählt werden, damit die Funktion \(y(x) = A + B e^{x^2/2}\) das Anfangswertproblem \(y' - xy - x = 0\), \(y(0) = 1\) löst?<ol type="a"><li>\(A = 2,\ B = -1\).</li><li>\(A = 1,\ B = 0\).</li><li>\(A = -1,\ B = 1\).</li><li>\(A = -1,\ B = 2\).</li></ol>
Back <b>(d)</b> \(A = -1,\ B = 2\).<br><br>Mit \(y = A + Be^{x^2/2}\) ist \(y' = Bx\,e^{x^2/2}\). Einsetzen in \(y' = xy + x = x(y+1)\): \(Bx\,e^{x^2/2} = x\left(A + 1 + Be^{x^2/2}\right)\). Der Term \(xBe^{x^2/2}\) hebt sich auf, es bleibt \(0 = x(A+1)\), also \(A = -1\). Die Anfangsbedingung \(y(0) = A + B = 1\) liefert \(B = 2\).
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::3._Lösungstechniken_erster_Ordnung::2._Substitution ETH::2._Semester::Analysis::Serie::13

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ETH::2._Semester::Analysis::6._Differentialgleichungen::5._Existenz_und_Eindeutigkeit
Satz von Picard-Lindelöf-Peano (Ordnung \(n\))
Das Anfangswertproblem
\[ \begin{gathered} y^{(n)} + f_{n-1}(x) y^{(n-1)} + \dots + f_1(x) y' + f_0(x) y = s(x) \\ y(x_0) = y_0,\ y'(x_0) = v_0,\ \dots,\ y^{(n-1)}(x_0) = z_0 \end{gathered} \]besitzt für "vernünftige" Funktionen \(f_{n-1}, \dots, f_0, s\) eine eindeutige Lösung \(x \mapsto y(x)\), \(x \in I\),
wobei \(I\) von \(x_0\) und den gegebenen Anfangsdaten abhängen kann.

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ETH::2._Semester::Analysis::6._Differentialgleichungen::5._Existenz_und_Eindeutigkeit
Satz von Picard-Lindelöf-Peano (Ordnung \(n\))
Das Anfangswertproblem
\[ \begin{gathered} y^{(n)} + f_{n-1}(x) y^{(n-1)} + \dots + f_1(x) y' + f_0(x) y = s(x) \\ y(x_0) = y_0,\ y'(x_0) = v_0,\ \dots,\ y^{(n-1)}(x_0) = z_0 \end{gathered} \]besitzt für "vernünftige" Funktionen \(f_{n-1}, \dots, f_0, s\) eine eindeutige Lösung \(x \mapsto y(x)\), \(x \in I\),
wobei \(I\) von \(x_0\) und den gegebenen Anfangsdaten abhängen kann.

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ETH::2._Semester::Analysis::6._Differentialgleichungen::5._Existenz_und_Eindeutigkeit
Satz von Picard-Lindelöf-Peano (Ordnung \(n\))
Das Anfangswertproblem
\[ \begin{gathered} y^{(n)} + f_{n-1}(x) y^{(n-1)} + \dots + f_1(x) y' + f_0(x) y = s(x) \\ y(x_0) = y_0,\ y'(x_0) = v_0,\ \dots,\ y^{(n-1)}(x_0) = z_0 \end{gathered} \]besitzt für "vernünftige" Funktionen \(f_{n-1}, \dots, f_0, s\) eine eindeutige Lösung \(x \mapsto y(x)\), \(x \in I\), wobei \(I\) von \(x_0\) und den gegebenen Anfangsdaten abhängen kann.

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ETH::2._Semester::Analysis::6._Differentialgleichungen::5._Existenz_und_Eindeutigkeit
Satz von Picard-Lindelöf-Peano (Ordnung \(n\))
Das Anfangswertproblem
\[ \begin{gathered} y^{(n)} + f_{n-1}(x) y^{(n-1)} + \dots + f_1(x) y' + f_0(x) y = s(x) \\ y(x_0) = y_0,\ y'(x_0) = v_0,\ \dots,\ y^{(n-1)}(x_0) = z_0 \end{gathered} \]besitzt für "vernünftige" Funktionen \(f_{n-1}, \dots, f_0, s\) eine eindeutige Lösung \(x \mapsto y(x)\), \(x \in I\), wobei \(I\) von \(x_0\) und den gegebenen Anfangsdaten abhängen kann.
Field-by-field Comparison
Field Before After
Text <b>Satz von Picard-Lindelöf-Peano (Ordnung \(n\))</b><br>Das Anfangswertproblem<br>\[ \begin{gathered} y^{(n)} + f_{n-1}(x) y^{(n-1)} + \dots + f_1(x) y' + f_0(x) y = s(x) \\ y(x_0) = y_0,\ y'(x_0) = v_0,\ \dots,\ y^{(n-1)}(x_0) = z_0 \end{gathered} \]besitzt für "vernünftige" Funktionen&nbsp;\(f_{n-1}, \dots, f_0, s\)&nbsp;{{c1::eine eindeutige Lösung}}&nbsp;\(x \mapsto y(x)\),&nbsp;\(x \in I\),<br>wobei&nbsp;\(I\)&nbsp;{{c2::von \(x_0\) und den gegebenen Anfangsdaten abhängen kann}}. <b>Satz von Picard-Lindelöf-Peano (Ordnung \(n\))</b><br>Das Anfangswertproblem<br>\[ \begin{gathered} y^{(n)} + f_{n-1}(x) y^{(n-1)} + \dots + f_1(x) y' + f_0(x) y = s(x) \\ y(x_0) = y_0,\ y'(x_0) = v_0,\ \dots,\ y^{(n-1)}(x_0) = z_0 \end{gathered} \]besitzt für "vernünftige" Funktionen&nbsp;\(f_{n-1}, \dots, f_0, s\)&nbsp;{{c1::eine eindeutige Lösung}}&nbsp;\(x \mapsto y(x)\),&nbsp;\(x \in I\), wobei&nbsp;\(I\)&nbsp;{{c2::von \(x_0\) und den gegebenen Anfangsdaten abhängen kann}}.
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::5._Existenz_und_Eindeutigkeit

Note 54: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::2._Folgen::3._Häufungspunkte
\(A \in \mathbb{R}\) ist ein Häufungspunkt einer Folge genau dann, wenn {{c1::eine konvergente Teilfolge \(({a_n}_k)_{k \in \mathbb{N_0} }\) existiert mit \[ \lim_{k \rightarrow \infty} {a_n}_k = A \]}}

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ETH::2._Semester::Analysis::2._Folgen::3._Häufungspunkte
\(A \in \mathbb{R}\) ist ein Häufungspunkt einer Folge genau dann, wenn {{c1::eine konvergente Teilfolge \(({a_n}_k)_{k \in \mathbb{N_0} }\) existiert mit \[ \lim_{k \rightarrow \infty} {a_n}_k = A \]}}

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ETH::2._Semester::Analysis::2._Folgen::3._Häufungspunkte
\(A \in \mathbb{R}\) ist ein Häufungspunkt einer Folge genau dann, wenn {{c1::eine konvergente Teilfolge \(({a_n}_k)_{k \in \mathbb{N_0} }\) existiert mit \[ \lim_{k \rightarrow \infty} {a_n}_k = A \]::Teilfolge}}

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ETH::2._Semester::Analysis::2._Folgen::3._Häufungspunkte
\(A \in \mathbb{R}\) ist ein Häufungspunkt einer Folge genau dann, wenn {{c1::eine konvergente Teilfolge \(({a_n}_k)_{k \in \mathbb{N_0} }\) existiert mit \[ \lim_{k \rightarrow \infty} {a_n}_k = A \]::Teilfolge}}
Field-by-field Comparison
Field Before After
Text \(A \in \mathbb{R}\) ist ein Häufungspunkt einer Folge genau dann, wenn {{c1::eine konvergente Teilfolge&nbsp;\(({a_n}_k)_{k \in \mathbb{N_0} }\) existiert mit \[ \lim_{k \rightarrow \infty} {a_n}_k = A \]}} \(A \in \mathbb{R}\) ist ein Häufungspunkt einer Folge genau dann, wenn {{c1::eine konvergente Teilfolge&nbsp;\(({a_n}_k)_{k \in \mathbb{N_0} }\) existiert mit \[ \lim_{k \rightarrow \infty} {a_n}_k = A \]::Teilfolge}}
Tags: ETH::2._Semester::Analysis::2._Folgen::3._Häufungspunkte

Note 55: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer Schwingung als Störfunktion
Störfunktion \(s(t) = A \sin(\omega t) + B \cos(\omega t)\):
\[ y(t) = C_1 \sin(\omega t) + C_2 \cos(\omega t) \]Spezialfall (Resonanz): Ist \(i\omega\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = (C_1 \sin(\omega t) + C_2 \cos(\omega t))\, t^m \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer Schwingung als Störfunktion
Störfunktion \(s(t) = A \sin(\omega t) + B \cos(\omega t)\):
\[ y(t) = C_1 \sin(\omega t) + C_2 \cos(\omega t) \]Spezialfall (Resonanz): Ist \(i\omega\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = (C_1 \sin(\omega t) + C_2 \cos(\omega t))\, t^m \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer Schwingung als Störfunktion
Störfunktion \(s(t) = A \sin(\omega t) + B \cos(\omega t)\):
\[ y(t) = C_1 \sin(\omega t) + C_2 \cos(\omega t) \]Spezialfall (Resonanz): Ist \(i\omega\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = (C_1 \sin(\omega t) + C_2 \cos(\omega t))\, t^m \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung
Ansatz für die partikuläre Lösung bei einer Schwingung als Störfunktion
Störfunktion \(s(t) = A \sin(\omega t) + B \cos(\omega t)\):
\[ y(t) = C_1 \sin(\omega t) + C_2 \cos(\omega t) \]Spezialfall (Resonanz): Ist \(i\omega\) eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz
\[ y(t) = (C_1 \sin(\omega t) + C_2 \cos(\omega t))\, t^m \]
Field-by-field Comparison
Field Before After
Text <b>Ansatz für die partikuläre Lösung</b> bei einer <b>Schwingung</b> als Störfunktion<br>Störfunktion&nbsp;\(s(t) = A \sin(\omega t) + B \cos(\omega t)\):<br>\[ y(t) = {{c1::C_1 \sin(\omega t) + C_2 \cos(\omega t)}} \]<b>Spezialfall</b> (Resonanz): Ist&nbsp;\(i\omega\)&nbsp;eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz<br>\[ y(t) = {{c2::(C_1 \sin(\omega t) + C_2 \cos(\omega t))\, t^m}} \] <b>Ansatz für die partikuläre Lösung</b> bei einer <b>Schwingung</b> als Störfunktion<br>Störfunktion&nbsp;\(s(t) = {{c1::A \sin(\omega t) + B \cos(\omega t)}}\):<br>\[ y(t) = {{c1::C_1 \sin(\omega t) + C_2 \cos(\omega t)}} \]<b>Spezialfall</b> (Resonanz): Ist&nbsp;\(i\omega\)&nbsp;eine \(m\)-fache Nullstelle des charakteristischen Polynoms, so lautet der Ansatz<br>\[ y(t) = {{c1::(C_1 \sin(\omega t) + C_2 \cos(\omega t))\, t^m}} \]
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::3._Ansatz_partikuläre_Lösung

Note 56: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::7._Integralrechnung::5._Integrierbarkeitskriterien ETH::2._Semester::Analysis::Serie::12
Sei \(f : [a,b] \to \mathbb{R}\) eine Funktion. Welche Aussagen sind richtig?
  1. \(f\) ist immer integrierbar.
  2. Falls \(f\) monoton ist, ist \(f\) auch integrierbar.
  3. Falls \(f\) beschränkt ist, ist \(f\) auch integrierbar.
  4. Falls \(f\) stetig ist, ist \(f\) auch integrierbar.

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ETH::2._Semester::Analysis::7._Integralrechnung::5._Integrierbarkeitskriterien ETH::2._Semester::Analysis::Serie::12
Sei \(f : [a,b] \to \mathbb{R}\) eine Funktion. Welche Aussagen sind richtig?
  1. \(f\) ist immer integrierbar.
  2. Falls \(f\) monoton ist, ist \(f\) auch integrierbar.
  3. Falls \(f\) beschränkt ist, ist \(f\) auch integrierbar.
  4. Falls \(f\) stetig ist, ist \(f\) auch integrierbar.

(b) und (d) sind richtig.

Monotone Funktionen und stetige Funktionen auf einem kompakten Intervall sind stets integrierbar. (a) ist falsch (nicht jede Funktion ist integrierbar) und (c) ist falsch (Beschränktheit genügt nicht, vgl. Dirichlet-Funktion).
Field-by-field Comparison
Field Before After
Front Sei \(f : [a,b] \to \mathbb{R}\) eine Funktion. Welche Aussagen sind richtig?<ol type="a"><li>\(f\) ist immer integrierbar.</li><li>Falls \(f\) monoton ist, ist \(f\) auch integrierbar.</li><li>Falls \(f\) beschränkt ist, ist \(f\) auch integrierbar.</li><li>Falls \(f\) stetig ist, ist \(f\) auch integrierbar.</li></ol>
Back <b>(b)</b> und <b>(d)</b> sind richtig.<br><br>Monotone Funktionen und stetige Funktionen auf einem kompakten Intervall sind stets integrierbar. (a) ist falsch (nicht jede Funktion ist integrierbar) und (c) ist falsch (Beschränktheit genügt nicht, vgl. Dirichlet-Funktion).
Tags: ETH::2._Semester::Analysis::7._Integralrechnung::5._Integrierbarkeitskriterien ETH::2._Semester::Analysis::Serie::12

Note 57: ETH::2. Semester::Analysis

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::1._Lösungsstruktur
Lösungsstruktur linearer, inhomogener DGl
Ist \(y_p(x)\) eine partikuläre Lösung der inhomogenen DGl und \(y_h(x)\) die allgemeine Lösung der dazugehörigen homogenen DGl, so ist die allgemeine Lösung der inhomogenen DGl
\[ y(x) = y_h(x) + y_p(x) \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::1._Lösungsstruktur
Lösungsstruktur linearer, inhomogener DGl
Ist \(y_p(x)\) eine partikuläre Lösung der inhomogenen DGl und \(y_h(x)\) die allgemeine Lösung der dazugehörigen homogenen DGl, so ist die allgemeine Lösung der inhomogenen DGl
\[ y(x) = y_h(x) + y_p(x) \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::1._Lösungsstruktur
Lösungsstruktur linearer, inhomogener DGl
Ist \(y_p(x)\) eine partikuläre Lösung der inhomogenen DGl und \(y_h(x)\) die allgemeine Lösung der dazugehörigen homogenen DGl, so ist die allgemeine Lösung der inhomogenen DGl
\[ y(x) = y_h(x) + y_p(x) \]

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ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::1._Lösungsstruktur
Lösungsstruktur linearer, inhomogener DGl
Ist \(y_p(x)\) eine partikuläre Lösung der inhomogenen DGl und \(y_h(x)\) die allgemeine Lösung der dazugehörigen homogenen DGl, so ist die allgemeine Lösung der inhomogenen DGl
\[ y(x) = y_h(x) + y_p(x) \]
Field-by-field Comparison
Field Before After
Text <b>Lösungsstruktur linearer, inhomogener DGl</b><br>Ist&nbsp;\(y_p(x)\)&nbsp;{{c1::eine partikuläre Lösung der inhomogenen DGl}} und&nbsp;\(y_h(x)\)&nbsp;{{c2::die allgemeine Lösung der dazugehörigen homogenen DGl}}, so ist die allgemeine Lösung der inhomogenen DGl<br>\[ y(x) = {{c3::y_h(x) + y_p(x)}} \] <b>Lösungsstruktur linearer, inhomogener DGl</b><br>Ist&nbsp;\(y_p(x)\)&nbsp;{{c1::eine partikuläre Lösung der inhomogenen DGl}} und&nbsp;\(y_h(x)\)&nbsp;{{c1::die allgemeine Lösung der dazugehörigen homogenen DGl}}, so ist die allgemeine Lösung der inhomogenen DGl<br>\[ y(x) = {{c3::y_h(x) + y_p(x)}} \]
Tags: ETH::2._Semester::Analysis::6._Differentialgleichungen::4._Lineare_inhomogene::1._Lösungsstruktur

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ETH::2._Semester::Analysis::7._Integralrechnung::4._Eigenschaften_bestimmtes_Integral ETH::2._Semester::Analysis::Serie::12
Welchen Wert hat das Integral \(\int_{-1}^{1} |x|\,dx\)?
  1. \(0\).
  2. \(\tfrac{1}{2}\).
  3. \(1\).
  4. \(2\).

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ETH::2._Semester::Analysis::7._Integralrechnung::4._Eigenschaften_bestimmtes_Integral ETH::2._Semester::Analysis::Serie::12
Welchen Wert hat das Integral \(\int_{-1}^{1} |x|\,dx\)?
  1. \(0\).
  2. \(\tfrac{1}{2}\).
  3. \(1\).
  4. \(2\).

(c) Der Wert ist \(1\).

\(\int_{-1}^{1} |x|\,dx = 2\int_{0}^{1} x\,dx = 2 \cdot \tfrac{1}{2} = 1\).
Field-by-field Comparison
Field Before After
Front Welchen Wert hat das Integral \(\int_{-1}^{1} |x|\,dx\)?<ol type="a"><li>\(0\).</li><li>\(\tfrac{1}{2}\).</li><li>\(1\).</li><li>\(2\).</li></ol>
Back <b>(c)</b> Der Wert ist \(1\).<br><br>\(\int_{-1}^{1} |x|\,dx = 2\int_{0}^{1} x\,dx = 2 \cdot \tfrac{1}{2} = 1\).
Tags: ETH::2._Semester::Analysis::7._Integralrechnung::4._Eigenschaften_bestimmtes_Integral ETH::2._Semester::Analysis::Serie::12

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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
ALU status flags: Z (result is zero), C (carry-out of the MSB), V (signed overflow), and N (negative/sign = MSB of the result).

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
ALU status flags: Z (result is zero), C (carry-out of the MSB), V (signed overflow), and N (negative/sign = MSB of the result).
Field-by-field Comparison
Field Before After
Text ALU status flags: {{c1::Z}} (result is zero), {{c2::C}} (carry-out of the MSB), {{c3::V}} (signed overflow), and {{c4::N}} (negative/sign = MSB of the result).
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 60: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms
For \(F(A,B,C)\) with the standard subscript convention, what is \(m_3\)?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms
For \(F(A,B,C)\) with the standard subscript convention, what is \(m_3\)?

\(\overline{A}BC\) - it is '1' only when \(ABC = 011\) (decimal 3).
Field-by-field Comparison
Field Before After
Front For \(F(A,B,C)\) with the standard subscript convention, what is \(m_3\)?
Back \(\overline{A}BC\) - it is '1' only when \(ABC = 011\) (decimal 3).
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms

Note 61: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
Why is the consensus term \(BC\) redundant in \(AB + \overline{A}C + BC\)?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
Why is the consensus term \(BC\) redundant in \(AB + \overline{A}C + BC\)?

If \(BC=1\) then \(B=C=1\). For either value of A, one of the other terms is already 1: A=1 gives AB=1, A=0 gives \(\overline{A}C=1\). So BC adds no new case.
Field-by-field Comparison
Field Before After
Front Why is the consensus term \(BC\) redundant in \(AB + \overline{A}C + BC\)?
Back If \(BC=1\) then \(B=C=1\). For either value of A, one of the other terms is already 1: A=1 gives AB=1, A=0 gives \(\overline{A}C=1\). So BC adds no new case.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

Note 62: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
How are 'don't care' conditions exploited in simplification?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
How are 'don't care' conditions exploited in simplification?

Each X may be treated as 1 to enlarge a group (yielding a simpler term) or as 0 if that helps more, giving extra flexibility for a simpler expression.
Field-by-field Comparison
Field Before After
Front How are 'don't care' conditions exploited in simplification?
Back Each X may be treated as 1 to enlarge a group (yielding a simpler term) or as 0 if that helps more, giving extra flexibility for a simpler expression.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

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ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
How do you build NOT, AND, and OR using only NAND gates?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
How do you build NOT, AND, and OR using only NAND gates?

NOT A = A NAND A; A AND B = NOT(A NAND B); A OR B = \(\overline{A}\) NAND \(\overline{B}\) (invert each input first, by De Morgan).
Field-by-field Comparison
Field Before After
Front How do you build NOT, AND, and OR using only NAND gates?
Back NOT A = A NAND A; A AND B = NOT(A NAND B); A OR B = \(\overline{A}\) NAND \(\overline{B}\) (invert each input first, by De Morgan).
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

Note 64: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
State the uniting (adjacency) theorem.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
State the uniting (adjacency) theorem.

\(AB + A\overline{B} = A\), and dually \((A+B)(A+\overline{B}) = A\). Two terms differing in exactly one variable (true vs complemented) merge and eliminate that variable.
Field-by-field Comparison
Field Before After
Front State the uniting (adjacency) theorem.
Back \(AB + A\overline{B} = A\), and dually \((A+B)(A+\overline{B}) = A\). Two terms differing in exactly one variable (true vs complemented) merge and eliminate that variable.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

Note 65: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
A gate set is logically complete if any Boolean function can be built from it alone.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
A gate set is logically complete if any Boolean function can be built from it alone.

Both NAND and NOR are individually complete.
Field-by-field Comparison
Field Before After
Text A gate set is {{c1::logically complete}} if any Boolean function can be built from it alone.
Extra Both NAND and NOR are individually complete.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
What is the purpose of a decoder's Enable input?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
What is the purpose of a decoder's Enable input?

When de-asserted it forces all outputs to their inactive state regardless of the address inputs; this allows gating and cascading of decoders.
Field-by-field Comparison
Field Before After
Front What is the purpose of a decoder's Enable input?
Back When de-asserted it forces all outputs to their inactive state regardless of the address inputs; this allows gating and cascading of decoders.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
In a priority encoder, once a higher-priority input is asserted the lower-priority inputs become don't cares for the output code.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
In a priority encoder, once a higher-priority input is asserted the lower-priority inputs become don't cares for the output code.
Field-by-field Comparison
Field Before After
Text In a priority encoder, once a higher-priority input is asserted the lower-priority inputs become {{c1::don't cares}} for the output code.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
What does a priority encoder output?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
What does a priority encoder output?

The binary index of the highest-priority active input, plus a Valid (V) output indicating whether any input is active.
Field-by-field Comparison
Field Before After
Front What does a priority encoder output?
Back The binary index of the highest-priority active input, plus a Valid (V) output indicating whether any input is active.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

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ETH::2._Semester::DDCA::01._Fundamentals
The Von Neumann model defines a computer by three essential components:
  1. computation (arithmetic/logic),
  2. communication (data transfer), and
  3. storage/memory.

Back

ETH::2._Semester::DDCA::01._Fundamentals
The Von Neumann model defines a computer by three essential components:
  1. computation (arithmetic/logic),
  2. communication (data transfer), and
  3. storage/memory.
Field-by-field Comparison
Field Before After
Text The Von Neumann model defines a computer by three essential components: <br><ol><li>{{c1::computation (arithmetic/logic)}}, </li><li>{{c2::communication (data transfer)}}, and </li><li>{{c3::storage/memory}}.</li></ol>
Tags: ETH::2._Semester::DDCA::01._Fundamentals

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ETH::2._Semester::DDCA::03._CMOS
A 2-input CMOS NAND uses 4 transistors and an inverter uses 2, so AND built as NAND + NOT uses 6 transistors.

Back

ETH::2._Semester::DDCA::03._CMOS
A 2-input CMOS NAND uses 4 transistors and an inverter uses 2, so AND built as NAND + NOT uses 6 transistors.
Field-by-field Comparison
Field Before After
Text A 2-input CMOS NAND uses {{c1::4}} transistors and an inverter uses {{c1::2}}, so AND built as NAND + NOT uses {{c1::6}} transistors.
Tags: ETH::2._Semester::DDCA::03._CMOS

Note 71: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::02._Transistors
n-type doping creates an excess of free electrons (negative carriers); p-type doping creates an excess of holes (positive carriers).

Back

ETH::2._Semester::DDCA::02._Transistors
n-type doping creates an excess of free electrons (negative carriers); p-type doping creates an excess of holes (positive carriers).
Field-by-field Comparison
Field Before After
Text n-type doping creates an excess of free {{c1::electrons (negative carriers)}}; p-type doping creates an excess of {{c1::holes (positive carriers)}}.
Tags: ETH::2._Semester::DDCA::02._Transistors

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ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms
What is a maxterm?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms
What is a maxterm?

A sum (OR) term in which all n variables appear exactly once (true or complemented); it is '0' for exactly one input combination.
Field-by-field Comparison
Field Before After
Front What is a maxterm?
Back A sum (OR) term in which all n variables appear exactly once (true or complemented); it is '0' for exactly one input combination.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms

Note 73: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::03._CMOS
A static CMOS gate has a pull-up network (PUN) of pMOS connecting the output to \(V_{dd}\), and a pull-down network (PDN) of nMOS connecting it to GND.

Back

ETH::2._Semester::DDCA::03._CMOS
A static CMOS gate has a pull-up network (PUN) of pMOS connecting the output to \(V_{dd}\), and a pull-down network (PDN) of nMOS connecting it to GND.
Field-by-field Comparison
Field Before After
Text A static CMOS gate has a {{c1::pull-up network (PUN)}} of pMOS connecting the output to \(V_{dd}\), and a {{c1::pull-down network (PDN)}} of nMOS connecting it to GND.
Tags: ETH::2._Semester::DDCA::03._CMOS

Note 74: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design
List the four steps of the combinational design process.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design
List the four steps of the combinational design process.

1) Functional specification (text, truth table, or equations). 2) Derive Boolean expressions. 3) Simplify (algebra or K-map). 4) Implement and map to gates.
Field-by-field Comparison
Field Before After
Front List the four steps of the combinational design process.
Back 1) Functional specification (text, truth table, or equations). 2) Derive Boolean expressions. 3) Simplify (algebra or K-map). 4) Implement and map to gates.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design

Note 75: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms
Minterm and maxterm of the same index are complementary: {{c1::\(\overline{m_i} = M_i\)}}.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms
Minterm and maxterm of the same index are complementary: {{c1::\(\overline{m_i} = M_i\)}}.
Field-by-field Comparison
Field Before After
Text Minterm and maxterm of the same index are complementary: {{c1::\(\overline{m_i} = M_i\)}}.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms

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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
How is a multi-bit ripple-carry adder built from full adders?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
How is a multi-bit ripple-carry adder built from full adders?

Cascade full adders, connecting each FA's \(C_{out}\) to the \(C_{in}\) of the next more significant stage.
Field-by-field Comparison
Field Before After
Front How is a multi-bit ripple-carry adder built from full adders?
Back Cascade full adders, connecting each FA's \(C_{out}\) to the \(C_{in}\) of the next more significant stage.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 77: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
State De Morgan's theorems.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
State De Morgan's theorems.

\(\overline{A+B} = \overline{A}\cdot\overline{B}\) (complement of a sum is the product of complements) and \(\overline{A\cdot B} = \overline{A}+\overline{B}\) (complement of a product is the sum of complements).
Field-by-field Comparison
Field Before After
Front State De Morgan's theorems.
Back \(\overline{A+B} = \overline{A}\cdot\overline{B}\) (complement of a sum is the product of complements) and \(\overline{A\cdot B} = \overline{A}+\overline{B}\) (complement of a product is the sum of complements).
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

Note 78: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::03._CMOS
Why is the PUN made of pMOS and the PDN of nMOS?

Back

ETH::2._Semester::DDCA::03._CMOS
Why is the PUN made of pMOS and the PDN of nMOS?

pMOS pass an undegraded '1' (\(V_{dd}\)), so they pull up strongly; nMOS pass an undegraded '0' (GND), so they pull down strongly.

Field-by-field Comparison
Field Before After
Front Why is the PUN made of pMOS and the PDN of nMOS?
Back pMOS pass an undegraded '1' (\(V_{dd}\)), so they pull up strongly; nMOS pass an undegraded '0' (GND), so they pull down strongly.<br><br><img alt="" src="Pasted-image-20250506151325.png">
Tags: ETH::2._Semester::DDCA::03._CMOS

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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
A tri-state buffer outputs A when Enable is asserted, and enters the high-impedance (Hi-Z) state when disabled, effectively disconnecting its output from the line.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
A tri-state buffer outputs A when Enable is asserted, and enters the high-impedance (Hi-Z) state when disabled, effectively disconnecting its output from the line.
Field-by-field Comparison
Field Before After
Text A tri-state buffer outputs A when Enable is asserted, and enters the {{c1::high-impedance (Hi-Z)}} state when disabled, effectively disconnecting its output from the line.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 80: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
Why are tri-state buffers essential for buses?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
Why are tri-state buffers essential for buses?

They let multiple devices share common data lines; enabling only one driver at a time prevents bus contention (collisions where drivers fight over the line).
Field-by-field Comparison
Field Before After
Front Why are tri-state buffers essential for buses?
Back They let multiple devices share common data lines; enabling only one driver at a time prevents bus contention (collisions where drivers fight over the line).
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 81: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
Which distributive law is unique to Boolean algebra (no arithmetic counterpart)?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
Which distributive law is unique to Boolean algebra (no arithmetic counterpart)?

OR distributes over AND: \(A + (B\cdot C) = (A+B)\cdot(A+C)\).
Field-by-field Comparison
Field Before After
Front Which distributive law is unique to Boolean algebra (no arithmetic counterpart)?
Back OR distributes over AND: \(A + (B\cdot C) = (A+B)\cdot(A+C)\).
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

Note 82: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
What does a decoder do?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
What does a decoder do?

Translates an n-bit input code into one of \(2^n\) outputs, asserting exactly one line ('one-hot'); output \(Y_i\) equals minterm \(m_i\) of the inputs.
Field-by-field Comparison
Field Before After
Front What does a decoder do?
Back Translates an n-bit input code into one of \(2^n\) outputs, asserting exactly one line ('one-hot'); output \(Y_i\) equals minterm \(m_i\) of the inputs.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
A 4-to-1 MUX output is \(Y = \overline{S_1}\,\overline{S_0}D_0 + \overline{S_1}S_0 D_1 + S_1\overline{S_0}D_2 + S_1 S_0 D_3\); each term ANDs a select-line minterm with its data input.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
A 4-to-1 MUX output is \(Y = \overline{S_1}\,\overline{S_0}D_0 + \overline{S_1}S_0 D_1 + S_1\overline{S_0}D_2 + S_1 S_0 D_3\); each term ANDs a select-line minterm with its data input.
Field-by-field Comparison
Field Before After
Text A 4-to-1 MUX output is \(Y = \overline{S_1}\,\overline{S_0}D_0 + \overline{S_1}S_0 D_1 + S_1\overline{S_0}D_2 + S_1 S_0 D_3\); each term ANDs a select-line {{c1::minterm}} with its data input.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

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ETH::2._Semester::DDCA::02._Transistors
In digital logic a high voltage \(V_{dd}\) represents '1' and a low voltage (GND) represents '0'.

Back

ETH::2._Semester::DDCA::02._Transistors
In digital logic a high voltage \(V_{dd}\) represents '1' and a low voltage (GND) represents '0'.
Field-by-field Comparison
Field Before After
Text In digital logic a high voltage \(V_{dd}\) represents {{c1::'1'}} and a low voltage (GND) represents {{c1::'0'}}.
Tags: ETH::2._Semester::DDCA::02._Transistors

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ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design
What are a PLA's two planes, and which are programmable?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design
What are a PLA's two planes, and which are programmable?

A programmable AND plane that generates product terms from inputs and their complements, and a programmable OR plane that sums selected product terms into SOP outputs.
Field-by-field Comparison
Field Before After
Front What are a PLA's two planes, and which are programmable?
Back A programmable AND plane that generates product terms from inputs and their complements, and a programmable OR plane that sums selected product terms into SOP outputs.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design

Note 86: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::03._CMOS
Why does static CMOS have very low static power dissipation?

Back

ETH::2._Semester::DDCA::03._CMOS
Why does static CMOS have very low static power dissipation?

The PUN and PDN are mutually exclusive, so for stable inputs there is never a direct conducting path from \(V_{dd}\) to GND.
Field-by-field Comparison
Field Before After
Front Why does static CMOS have very low static power dissipation?
Back The PUN and PDN are mutually exclusive, so for stable inputs there is never a direct conducting path from \(V_{dd}\) to GND.
Tags: ETH::2._Semester::DDCA::03._CMOS

Note 87: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
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GUID: ^5@qC?]Wi6
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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
What does a multiplexer (MUX) do?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
What does a multiplexer (MUX) do?

Selects one of \(2^n\) data inputs and routes it to a single output; the choice is made by n select lines (a data selector).
Field-by-field Comparison
Field Before After
Front What does a multiplexer (MUX) do?
Back Selects one of \(2^n\) data inputs and routes it to a single output; the choice is made by n select lines (a data selector).
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 88: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: b}(FC;F#gT
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ETH::2._Semester::DDCA
This is a test card.

Back

ETH::2._Semester::DDCA
This is a test card.
Field-by-field Comparison
Field Before After
Text This is a {{c1::test}} card.
Tags: ETH::2._Semester::DDCA

Note 89: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
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GUID: cuWyu+uZAU
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ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
State the duality principle.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
State the duality principle.

A valid Boolean equation stays valid if you swap every AND with OR and every 0 with 1, leaving variables and their complements unchanged.
Field-by-field Comparison
Field Before After
Front State the duality principle.
Back A valid Boolean equation stays valid if you swap every AND with OR and every 0 with 1, leaving variables and their complements unchanged.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

Note 90: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: d+J
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Front

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
How is subtraction typically implemented in an ALU?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
How is subtraction typically implemented in an ALU?

As addition of the 2's complement of the subtrahend, reusing the adder hardware.
Field-by-field Comparison
Field Before After
Front How is subtraction typically implemented in an ALU?
Back As addition of the 2's complement of the subtrahend, reusing the adder hardware.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 91: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: g?x3XM0iva
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Front

ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design
How is an SOP expression implemented with gates (two-level)?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design
How is an SOP expression implemented with gates (two-level)?

One AND gate per product term, then all AND-gate outputs feed a single OR gate that produces the output F.
Field-by-field Comparison
Field Before After
Front How is an SOP expression implemented with gates (two-level)?
Back One AND gate per product term, then all AND-gate outputs feed a single OR gate that produces the output F.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design

Note 92: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: gP:bKN8YdD
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Front

ETH::2._Semester::DDCA
What is this card?

Back

ETH::2._Semester::DDCA
What is this card?

A test card.
Field-by-field Comparison
Field Before After
Front What is this card?
Back A test card.
Tags: ETH::2._Semester::DDCA

Note 93: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: i,@zxTDf(J
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Front

ETH::2._Semester::DDCA::01._Fundamentals
What three quantities does computer architecture seek to balance?

Back

ETH::2._Semester::DDCA::01._Fundamentals
What three quantities does computer architecture seek to balance?

Performance, energy efficiency, and cost-effectiveness.
Field-by-field Comparison
Field Before After
Front What three quantities does computer architecture seek to balance?
Back Performance, energy efficiency, and cost-effectiveness.
Tags: ETH::2._Semester::DDCA::01._Fundamentals

Note 94: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: jZY7GAX^4P
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Front

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
What is a Karnaugh map and what is it useful for?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
What is a Karnaugh map and what is it useful for?

A graphical rearrangement of a truth table that places adjacent terms next to each other, making the uniting theorem visible via grouping; practical for up to about 4-5 variables.
Field-by-field Comparison
Field Before After
Front What is a Karnaugh map and what is it useful for?
Back A graphical rearrangement of a truth table that places adjacent terms next to each other, making the uniting theorem visible via grouping; practical for up to about 4-5 variables.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

Note 95: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: kuH>y#ZF-(
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Front

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
State the consensus theorem (SOP form).

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
State the consensus theorem (SOP form).

\(AB + \overline{A}C + BC = AB + \overline{A}C\); the consensus term \(BC\) is redundant.
Field-by-field Comparison
Field Before After
Front State the consensus theorem (SOP form).
Back \(AB + \overline{A}C + BC = AB + \overline{A}C\); the consensus term \(BC\) is redundant.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

Note 96: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: lJ?@CZya!U
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Front

ETH::2._Semester::DDCA::02._Transistors
When does an nMOS transistor conduct?

Back

ETH::2._Semester::DDCA::02._Transistors
When does an nMOS transistor conduct?

When its gate is HIGH relative to the source (exceeding the threshold \(V_T\)), forming an n-channel. High gate voltage -> conducts.
Field-by-field Comparison
Field Before After
Front When does an nMOS transistor conduct?
Back When its gate is HIGH relative to the source (exceeding the threshold \(V_T\)), forming an n-channel. High gate voltage -> conducts.
Tags: ETH::2._Semester::DDCA::02._Transistors

Note 97: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: lSE+u10=7`
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ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
Combinational logic outputs depend only on current inputs (memoryless, like a pure function), whereas sequential logic outputs also depend on stored past state.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra
Combinational logic outputs depend only on current inputs (memoryless, like a pure function), whereas sequential logic outputs also depend on stored past state.
Field-by-field Comparison
Field Before After
Text {{c1::Combinational}} logic outputs depend only on current inputs (memoryless, like a pure function), whereas {{c2::sequential}} logic outputs also depend on stored past state.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::1._Boolean_Algebra

Note 98: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: m!IP3L
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ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
Give the 1-bit comparator logic for A>B, A=B, and A<B.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
Give the 1-bit comparator logic for A>B, A=B, and A<B.

\(G\;(A>B) = A\overline{B}\); \(E\;(A=B) = \overline{A\oplus B}\) (XNOR); \(L\;(A<B) = \overline{A}B\).
Field-by-field Comparison
Field Before After
Front Give the 1-bit comparator logic for A&gt;B, A=B, and A&lt;B.
Back \(G\;(A&gt;B) = A\overline{B}\); \(E\;(A=B) = \overline{A\oplus B}\) (XNOR); \(L\;(A&lt;B) = \overline{A}B\).
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 99: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: mKYqB$]gl6
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Front

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
Full adder sum \(S = A \oplus B \oplus C_{in}\) (1 for an odd number of 1s); carry-out \(C_{out} = AB + AC_{in} + BC_{in}\) (1 when two or more inputs are 1, i.e. majority).

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
Full adder sum \(S = A \oplus B \oplus C_{in}\) (1 for an odd number of 1s); carry-out \(C_{out} = AB + AC_{in} + BC_{in}\) (1 when two or more inputs are 1, i.e. majority).
Field-by-field Comparison
Field Before After
Text Full adder sum \(S = A \oplus B \oplus C_{in}\) (1 for an {{c1::odd}} number of 1s); carry-out \(C_{out} = AB + AC_{in} + BC_{in}\) (1 when {{c2::two or more}} inputs are 1, i.e. majority).
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 100: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: oOT:-B{CG4
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ETH::2._Semester::DDCA::02._Transistors
pMOS transistors are strong '1' passers but weak '0' passers.

Back

ETH::2._Semester::DDCA::02._Transistors
pMOS transistors are strong '1' passers but weak '0' passers.

(a passed low only reaches \(GND + |V_{Tp}|\))
Field-by-field Comparison
Field Before After
Text pMOS transistors are strong {{c1::'1'}} passers but weak {{c1::'0'}} passers.
Extra (a passed low only reaches&nbsp;\(GND + |V_{Tp}|\))
Tags: ETH::2._Semester::DDCA::02._Transistors

Note 101: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: p*YvfZm2F!
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ETH::2._Semester::DDCA::03._CMOS
In a 2-input CMOS NAND gate, how are the transistors arranged?

Back

ETH::2._Semester::DDCA::03._CMOS
In a 2-input CMOS NAND gate, how are the transistors arranged?



PUN: two pMOS in parallel.
PDN: two nMOS in series.

Output is '0' only when both inputs are '1'.
Field-by-field Comparison
Field Before After
Front In a 2-input CMOS NAND gate, how are the transistors arranged?
Back <img alt="" src="Pasted-image-20250506151307.png"><br><br>PUN: two pMOS in parallel. <br>PDN: two nMOS in series. <br><br>Output is '0' only when both inputs are '1'.
Tags: ETH::2._Semester::DDCA::03._CMOS

Note 102: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: pcG^^H1T)5
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Front

ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms
Canonical SOP = OR of all minterms where F = 1; canonical POS = AND of all maxterms where F = 0.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms
Canonical SOP = OR of all minterms where F = 1; canonical POS = AND of all maxterms where F = 0.
Field-by-field Comparison
Field Before After
Text Canonical SOP = OR of all {{c1::minterms}} where F = 1; canonical POS = AND of all {{c2::maxterms}} where F = 0.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms

Note 103: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: prd;?q]|(^
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Front

ETH::2._Semester::DDCA::03._CMOS
Why is AND typically built as NAND + NOT rather than directly?

Back

ETH::2._Semester::DDCA::03._CMOS
Why is AND typically built as NAND + NOT rather than directly?

NAND/NOR have compact regular CMOS structures, are faster (series nMOS beats slower series pMOS), and are universal, so standard cell libraries optimize them.
Field-by-field Comparison
Field Before After
Front Why is AND typically built as NAND + NOT rather than directly?
Back NAND/NOR have compact regular CMOS structures, are faster (series nMOS beats slower series pMOS), and are universal, so standard cell libraries optimize them.
Tags: ETH::2._Semester::DDCA::03._CMOS

Note 104: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: t!D$a@JudH
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Front

ETH::2._Semester::DDCA::02._Transistors
When does a pMOS transistor conduct?

Back

ETH::2._Semester::DDCA::02._Transistors
When does a pMOS transistor conduct?

When its gate is LOW relative to the source (below by more than \(|V_{Tp}|\)), forming a p-channel. Low gate voltage -> conducts.
Field-by-field Comparison
Field Before After
Front When does a pMOS transistor conduct?
Back When its gate is LOW relative to the source (below by more than \(|V_{Tp}|\)), forming a p-channel. Low gate voltage -&gt; conducts.
Tags: ETH::2._Semester::DDCA::02._Transistors

Note 105: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: tn9D_Q-!W_
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ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design
A key efficiency of PLAs: shared product terms are generated once in the AND plane and reused by multiple OR gates in the OR plane.

Back

ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design
A key efficiency of PLAs: shared product terms are generated once in the AND plane and reused by multiple OR gates in the OR plane.
Field-by-field Comparison
Field Before After
Text A key efficiency of PLAs: shared {{c1::product terms}} are generated once in the AND plane and reused by multiple OR gates in the OR plane.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::3._Combinational_Design

Note 106: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: vbjjEgJmG#
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Front

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
How can a MUX implement an arbitrary Boolean function?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
How can a MUX implement an arbitrary Boolean function?

Tie its data inputs to '0', '1', or a variable according to the function's truth table, using the select lines as the function's input variables.
Field-by-field Comparison
Field Before After
Front How can a MUX implement an arbitrary Boolean function?
Back Tie its data inputs to '0', '1', or a variable according to the function's truth table, using the select lines as the function's input variables.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 107: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: vtk`Fgy_WB
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Front

ETH::2._Semester::DDCA::01._Fundamentals
Accessing memory costs roughly 6400x the energy of a simple computation, which drives the performance-power tradeoff.

Back

ETH::2._Semester::DDCA::01._Fundamentals
Accessing memory costs roughly 6400x the energy of a simple computation, which drives the performance-power tradeoff.
Field-by-field Comparison
Field Before After
Text Accessing memory costs roughly {{c1::6400x}} the energy of a simple computation, which drives the performance-power tradeoff.
Tags: ETH::2._Semester::DDCA::01._Fundamentals

Note 108: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: vuS!^8.^&n
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Front

ETH::2._Semester::DDCA::02._Transistors
What are the roles of a MOSFET's three terminals?

Back

ETH::2._Semester::DDCA::02._Transistors
What are the roles of a MOSFET's three terminals?

Gate (G): control input whose voltage switches the device ON/OFF.
Source (S) and Drain (D): terminals between which current flows when the device is ON.

Field-by-field Comparison
Field Before After
Front What are the roles of a MOSFET's three terminals?
Back Gate (G): control input whose voltage switches the device ON/OFF. <br>Source (S) and Drain (D): terminals between which current flows when the device is ON.<br><br><img alt="" src="Pasted-image-20250506151131.png">
Tags: ETH::2._Semester::DDCA::02._Transistors

Note 109: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: wqj}Lq{!Zy
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Front

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
How do you determine A>B for two multi-bit numbers?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
How do you determine A>B for two multi-bit numbers?

Scan from the most significant bit: A>B at the first (highest) position i where \(A_i=1\) and \(B_i=0\), with all more significant bits equal.
Field-by-field Comparison
Field Before After
Front How do you determine A&gt;B for two multi-bit numbers?
Back Scan from the most significant bit: A&gt;B at the first (highest) position i where \(A_i=1\) and \(B_i=0\), with all more significant bits equal.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 110: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: z_98Q7m<>v
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Front

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
What does an ALU do, and what selects its operation?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components
What does an ALU do, and what selects its operation?

It performs arithmetic (add, subtract, increment, decrement) and bitwise logic (AND, OR, XOR, NOT) on operands; the operation is chosen by control/opcode (function-select) lines.
Field-by-field Comparison
Field Before After
Front What does an ALU do, and what selects its operation?
Back It performs arithmetic (add, subtract, increment, decrement) and bitwise logic (AND, OR, XOR, NOT) on operands; the operation is chosen by control/opcode (function-select) lines.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::4._Combinational_Components

Note 111: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: {&2aK<+i#H
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Front

ETH::2._Semester::DDCA::02._Transistors
nMOS transistors are strong '0' passers but weak '1' passers.

Back

ETH::2._Semester::DDCA::02._Transistors
nMOS transistors are strong '0' passers but weak '1' passers.

(a passed high only reaches \(V_{dd} - V_T\))
Field-by-field Comparison
Field Before After
Text nMOS transistors are strong {{c1::'0'}} passers but weak {{c1::'1'}} passers.
Extra (a passed high only reaches&nbsp;\(V_{dd} - V_T\))
Tags: ETH::2._Semester::DDCA::02._Transistors

Note 112: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: |_q:eS/GP*
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Front

ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms
What is a minterm?

Back

ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms
What is a minterm?

A product (AND) term in which all n variables appear exactly once (true or complemented); it is '1' for exactly one input combination. There are \(2^n\) minterms.
Field-by-field Comparison
Field Before After
Front What is a minterm?
Back A product (AND) term in which all n variables appear exactly once (true or complemented); it is '1' for exactly one input combination. There are \(2^n\) minterms.
Tags: ETH::2._Semester::DDCA::04._Digital_Logic::2._Canonical_Forms

Note 113: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: }`~+a2h3/)
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Front

ETH::2._Semester::DDCA::01._Fundamentals
Name the computing-system abstraction layers from bottom to top.

Back

ETH::2._Semester::DDCA::01._Fundamentals
Name the computing-system abstraction layers from bottom to top.

Physical devices (electrons) -> logic -> microarchitecture (e.g. x86, ARM) -> ISA -> system software -> algorithms/problems.
Field-by-field Comparison
Field Before After
Front Name the computing-system abstraction layers from bottom to top.
Back Physical devices (electrons) -&gt; logic -&gt; microarchitecture (e.g. x86, ARM) -&gt; ISA -&gt; system software -&gt; algorithms/problems.
Tags: ETH::2._Semester::DDCA::01._Fundamentals

Note 114: ETH::2. Semester::PProg

Deck: ETH::2. Semester::PProg
Note Type: Horvath Cloze
GUID: $zyCmI+(er
modified

Before

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Software TM (STM): implemented in the (parallel) programming language, offers greater flexibility, but achieving good performance can be challenging. Examples: Haskell, Clojure. Hybrid TM (hardware + software) is currently a research topic.

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Software TM (STM): implemented in the (parallel) programming language, offers greater flexibility, but achieving good performance can be challenging. Examples: Haskell, Clojure. Hybrid TM (hardware + software) is currently a research topic.

STM implementations are still actively developed, whereas pure HTM (RTM) barely succeeded in the market. Overall, TM is still work in progress.

After

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Software TM (STM): implemented in the (parallel) programming language, offers greater flexibility, but achieving good performance can be challenging.

Examples: Haskell, Clojure.

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Software TM (STM): implemented in the (parallel) programming language, offers greater flexibility, but achieving good performance can be challenging.

Examples: Haskell, Clojure.

Hybrid TM (hardware + software) is currently a research topic.

STM implementations are still actively developed, whereas pure HTM (RTM) barely succeeded in the market. Overall, TM is still work in progress.
Field-by-field Comparison
Field Before After
Text Software TM (STM): implemented in the (parallel) programming language, offers {{c1::greater flexibility}}, but {{c2::achieving good performance can be challenging}}. Examples: Haskell, Clojure. Hybrid TM (hardware + software) is currently a {{c3::research topic}}. Software TM (STM): implemented in the (parallel) programming language, offers {{c1::greater flexibility}}, but {{c1::achieving good performance can be challenging}}. <br><br>Examples: Haskell, Clojure.
Extra STM implementations are still actively developed, whereas pure HTM (RTM) barely succeeded in the market. Overall, TM is still work in progress. Hybrid TM (hardware + software) is currently a research topic.<br><br>STM implementations are still actively developed, whereas pure HTM (RTM) barely succeeded in the market. Overall, TM is still work in progress.
Tags: ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation

Note 115: ETH::2. Semester::PProg

Deck: ETH::2. Semester::PProg
Note Type: Horvath Cloze
GUID: 5jCCKEp1WY
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Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Zombies and consistency (initially a = 10, b = 0, c = 0): TXA computes c = 1 / (a-b), TXB commits with a = 0, b = 10. If TXA inconsistently read the already-committed b = 10 (but kept the old a), then a-b = 0, giving a division by zero (catastrophic inconsistency). Guarantee of the TM system: a running transaction is always shown consistent data. Conceptual possibilities: snapshot at the beginning or early abort.

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Zombies and consistency (initially a = 10, b = 0, c = 0): TXA computes c = 1 / (a-b), TXB commits with a = 0, b = 10. If TXA inconsistently read the already-committed b = 10 (but kept the old a), then a-b = 0, giving a division by zero (catastrophic inconsistency). Guarantee of the TM system: a running transaction is always shown consistent data. Conceptual possibilities: snapshot at the beginning or early abort.

A zombie is a doomed (later aborted) transaction that transiently sees inconsistent data. Without a consistency guarantee it could cause damage (e.g. crash, infinite loop) before it is even aborted.

After

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Zombies and consistency



TXA computes c = 1 / (a-b), TXB commits with a = 0, b = 10. If TXA inconsistently read the already-committed b = 10 (but kept the old a), then a-b = 0, giving a division by zero (catastrophic inconsistency).

Guarantee of the TM system: a running transaction is always shown consistent data.

Conceptual possibilities: snapshot at the beginning or early abort.

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Zombies and consistency



TXA computes c = 1 / (a-b), TXB commits with a = 0, b = 10. If TXA inconsistently read the already-committed b = 10 (but kept the old a), then a-b = 0, giving a division by zero (catastrophic inconsistency).

Guarantee of the TM system: a running transaction is always shown consistent data.

Conceptual possibilities: snapshot at the beginning or early abort.

A zombie is a doomed (later aborted) transaction that transiently sees inconsistent data. Without a consistency guarantee it could cause damage (e.g. crash, infinite loop) before it is even aborted.
Field-by-field Comparison
Field Before After
Text Zombies and consistency (initially a = 10, b = 0, c = 0): TXA computes c = 1 / (a-b), TXB commits with a = 0, b = 10. If TXA inconsistently read the already-committed b = 10 (but kept the old a), then a-b = 0, giving a {{c1::division by zero (catastrophic inconsistency)}}. Guarantee of the TM system: a running transaction is always shown {{c2::consistent data}}. Conceptual possibilities: {{c3::snapshot at the beginning}} or {{c3::early abort}}. Zombies and consistency<br><br><img src="paste-dda11d70d836d2be1276dd57354664dafd047f76.jpg"><br><br>TXA computes c = 1 / (a-b), TXB commits with a = 0, b = 10. If TXA inconsistently read the already-committed b = 10 (but kept the old a), then a-b = 0, giving a {{c1::division by zero (catastrophic inconsistency)}}. <br><br>Guarantee of the TM system: a running transaction is always shown {{c2::consistent data}}. <br><br>Conceptual possibilities: {{c3::snapshot at the beginning}} or {{c3::early abort}}.
Tags: ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation

Note 116: ETH::2. Semester::PProg

Deck: ETH::2. Semester::PProg
Note Type: Horvath Classic
GUID: 6.;IeGU,Ik
modified

Before

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
What does the bank account look like in ScalaSTM (on Java), and why use new Runnable() instead of just atomic?

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
What does the bank account look like in ScalaSTM (on Java), and why use new Runnable() instead of just atomic?

The mutable balance lives in a Ref:
class AccountSTM {
    private final Integer id;
    private final Ref.View<Integer> balance;
    AccountSTM(int id, int balance) {
        this.id = new Integer(id);
        this.balance = STM.newRef(balance);
    }
}
Ideal world with an atomic keyword:
void withdraw(final int amount) {
    atomic {
        int old_val = balance.get();
        balance.set(old_val - amount);
    }
}
Real ScalaSTM version (Java 7 has no lambdas), each transaction is a Runnable:
void withdraw(final int amount) {
    STM.atomic(new Runnable() { public void run() {
        int old_val = balance.get();
        balance.set(old_val - amount);
    }});
}
There is also no compiler support enforcing that Refs are only accessed inside a transaction.

After

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
What does the bank account look like in ScalaSTM (on Java), and why use new Runnable() instead of just atomic?

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
What does the bank account look like in ScalaSTM (on Java), and why use new Runnable() instead of just atomic?

The mutable balance lives in a Ref:



Ideal world with an atomic keyword:



Real ScalaSTM version (Java 7 has no lambdas), each transaction is a Runnable:



There is also no compiler support enforcing that Refs are only accessed inside a transaction.
Field-by-field Comparison
Field Before After
Back The mutable balance lives in a Ref: <pre>class AccountSTM { private final Integer id; private final Ref.View&lt;Integer&gt; balance; AccountSTM(int id, int balance) { this.id = new Integer(id); this.balance = STM.newRef(balance); } }</pre>Ideal world with an atomic keyword: <pre>void withdraw(final int amount) { atomic { int old_val = balance.get(); balance.set(old_val - amount); } }</pre>Real ScalaSTM version (Java 7 has no lambdas), each transaction is a Runnable: <pre>void withdraw(final int amount) { STM.atomic(new Runnable() { public void run() { int old_val = balance.get(); balance.set(old_val - amount); }}); }</pre>There is also no compiler support enforcing that Refs are only accessed inside a transaction. The mutable balance lives in a Ref:<br><br><img src="paste-914be56408d35805bcd2165d0544d9038c79d76a.jpg"><br><br>Ideal world with an atomic keyword:<br><br><img src="paste-b0c20a9f6eb8fb3456bd8623f1ae73106690cdf6.jpg"><br><br>Real ScalaSTM version (Java 7 has no lambdas), each transaction is a Runnable:<br><br><img src="paste-e8d8b7ac4f32e73bfbf7d48d53c4897b4eb2e94b.jpg"><br><br>There is also no compiler support enforcing that Refs are only accessed inside a transaction.
Tags: ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation

Note 117: ETH::2. Semester::PProg

Deck: ETH::2. Semester::PProg
Note Type: Horvath Cloze
GUID: L@08r/Uv,l
modified

Before

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Implementing TM, two approaches: (1) a big lock around all atomic sections: gives (nearly) all desired properties but is not scalable and is not done in practice. (2) keep track of the operations performed by each transaction (concurrency control): the system guarantees atomicity and isolation.

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Implementing TM, two approaches: (1) a big lock around all atomic sections: gives (nearly) all desired properties but is not scalable and is not done in practice. (2) keep track of the operations performed by each transaction (concurrency control): the system guarantees atomicity and isolation.

With the big lock, the missing property is mainly scalability (concurrent transactions cannot run in parallel).

After

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Implementing TM, two approaches:
  1. A big lock around all atomic sections: gives (nearly) all desired properties but is not scalable and is not done in practice.
  2. Keep track of the operations performed by each transaction (concurrency control): the system guarantees atomicity and isolation.

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Implementing TM, two approaches:
  1. A big lock around all atomic sections: gives (nearly) all desired properties but is not scalable and is not done in practice.
  2. Keep track of the operations performed by each transaction (concurrency control): the system guarantees atomicity and isolation.

With the big lock, the missing property is mainly scalability (concurrent transactions cannot run in parallel).
Field-by-field Comparison
Field Before After
Text Implementing TM, two approaches: (1) a {{c1::big lock around all atomic sections}}: gives (nearly) all desired properties but is {{c1::not scalable}} and is not done in practice. (2) keep track of the operations performed by each transaction ({{c2::concurrency control}}): the system guarantees {{c2::atomicity and isolation}}. Implementing TM, two approaches: <br><ol><li>{{c1::A big lock around all atomic sections: gives (nearly) all desired properties but is not scalable and is not done in practice}}. </li><li>{{c2::Keep track of the operations performed by each transaction (concurrency control): the system guarantees atomicity and isolation}}.</li></ol>
Tags: ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation

Note 118: ETH::2. Semester::PProg

Deck: ETH::2. Semester::PProg
Note Type: Horvath Cloze
GUID: TrD0i9G.}s
modified

Before

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Hardware TM (HTM): can be fast but has bounded resources and often cannot handle big transactions. The first widely available x86 implementation was Intel's Haswell (RTM), which was largely removed soon after. The Haswell instructions are xbegin (begin transaction), xend (end), xabort (abort).

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Hardware TM (HTM): can be fast but has bounded resources and often cannot handle big transactions. The first widely available x86 implementation was Intel's Haswell (RTM), which was largely removed soon after. The Haswell instructions are xbegin (begin transaction), xend (end), xabort (abort).

Other HTM examples: Sun/Oracle Rock (never released), IBM Blue Gene/Q (long retired). Pattern: xbegin L0 / transaction code / xend; on abort, execution jumps to L0.

After

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Hardware TM (HTM): can be fast but has bounded resources and often cannot handle big transactions.

The first widely available x86 implementation was Intel's Haswell (RTM), which was largely removed soon after. 

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Hardware TM (HTM): can be fast but has bounded resources and often cannot handle big transactions.

The first widely available x86 implementation was Intel's Haswell (RTM), which was largely removed soon after. 

The Haswell instructions are xbegin (begin transaction), xend (end), xabort (abort).

Other HTM examples: Sun/Oracle Rock (never released), IBM Blue Gene/Q (long retired). Pattern: xbegin L0 / transaction code / xend; on abort, execution jumps to L0.
Field-by-field Comparison
Field Before After
Text Hardware TM (HTM): {{c1::can be fast but has bounded resources and often cannot handle big transactions}}. The first widely available x86 implementation was {{c2::Intel's Haswell (RTM)}}, which was largely removed soon after. The Haswell instructions are {{c3::xbegin (begin transaction), xend (end), xabort (abort)}}. Hardware TM (HTM): {{c1::can be fast but has bounded resources and often cannot handle big transactions::Pros and Cons}}. <br><br>The first widely available x86 implementation was {{c2::Intel's Haswell (RTM)}}, which was largely removed soon after.&nbsp;
Extra Other HTM examples: Sun/Oracle Rock (never released), IBM Blue Gene/Q (long retired). Pattern: xbegin L0 / transaction code / xend; on abort, execution jumps to L0. The Haswell instructions are xbegin (begin transaction), xend (end), xabort (abort).<br><br>Other HTM examples: Sun/Oracle Rock (never released), IBM Blue Gene/Q (long retired). Pattern: xbegin L0 / transaction code / xend; on abort, execution jumps to L0.
Tags: ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation

Note 119: ETH::2. Semester::PProg

Deck: ETH::2. Semester::PProg
Note Type: Horvath Cloze
GUID: _Z&YGuT-Pb
modified

Before

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Nesting semantics for nested transactions (important for composability). Flat nesting: all levels are merged into one transaction, so an inner abort aborts the outer and an inner commit is visible only if the outer commits. Closed nesting (similar, but): an abort of an inner transaction does not abort the outer; an inner commit makes changes visible to the outer transaction but not to other transactions, and only the commit of the outer makes them globally visible.

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Nesting semantics for nested transactions (important for composability). Flat nesting: all levels are merged into one transaction, so an inner abort aborts the outer and an inner commit is visible only if the outer commits. Closed nesting (similar, but): an abort of an inner transaction does not abort the outer; an inner commit makes changes visible to the outer transaction but not to other transactions, and only the commit of the outer makes them globally visible.

Another approach: open nesting. Nested transactions are the prerequisite for atomic blocks to be composable.

After

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Nesting semantics for nested transactions (important for composability).

Flat nesting: all levels are merged into one transaction, so an inner abort aborts the outer and an inner commit is visible only if the outer commits.

Closed nesting (similar, but): an abort of an inner transaction does not abort the outer; an inner commit makes changes visible to the outer transaction but not to other transactions, and only the commit of the outer makes them globally visible.

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Nesting semantics for nested transactions (important for composability).

Flat nesting: all levels are merged into one transaction, so an inner abort aborts the outer and an inner commit is visible only if the outer commits.

Closed nesting (similar, but): an abort of an inner transaction does not abort the outer; an inner commit makes changes visible to the outer transaction but not to other transactions, and only the commit of the outer makes them globally visible.

Another approach: open nesting. Nested transactions are the prerequisite for atomic blocks to be composable.
Field-by-field Comparison
Field Before After
Text Nesting semantics for nested transactions (important for composability). Flat nesting: all levels are merged into one transaction, so {{c1::an inner abort aborts the outer}} and an inner commit is {{c1::visible only if the outer commits}}. Closed nesting (similar, but): {{c2::an abort of an inner transaction does not abort the outer}}; an inner commit makes changes {{c2::visible to the outer transaction but not to other transactions}}, and only the commit of the outer makes them {{c2::globally visible}}. Nesting semantics for nested transactions (important for composability). <br><br>Flat nesting: all levels are merged into one transaction, so an inner abort {{c1::aborts the outer}} and an inner commit is {{c2::visible only if the outer commits}}. <br><br>Closed nesting (similar, but): an abort of an inner transaction {{c1::does not abort the outer}}; an inner commit makes changes {{c2::visible to the outer transaction but not to other transactions}}, and only the commit of the outer makes them {{c2::globally visible}}.
Tags: ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation

Note 120: ETH::2. Semester::PProg

Deck: ETH::2. Semester::PProg
Note Type: Horvath Classic
GUID: j&UK790c$]
modified

Before

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Conflict example (initially a = 0): TXA reads x = a, TXB writes a = 10 and then commits. Question: may TXA be placed after TXB in the serialization order if TXA still read a == 0? Answer: . In the serial order TXB then TXA, TXA would have to ; executions that read a == 0 are .

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Conflict example (initially a = 0): TXA reads x = a, TXB writes a = 10 and then commits. Question: may TXA be placed after TXB in the serialization order if TXA still read a == 0? Answer: . In the serial order TXB then TXA, TXA would have to ; executions that read a == 0 are .

A transaction's local writes become visible to others only after commit. Such a read-write conflict is detected and handled by the concurrency-control mechanism.

After

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation


May TXA be placed after TXB in the serialization order if TXA still read a == 0?

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation


May TXA be placed after TXB in the serialization order if TXA still read a == 0?

No.

In the serial order TXB then TXA, TXA would have to read a == 10; executions that read a == 0 are invalid.

A transaction's local writes become visible to others only after commit. Such a read-write conflict is detected and handled by the concurrency-control mechanism.
Field-by-field Comparison
Field Before After
Front Conflict example (initially a = 0): TXA reads x = a, TXB writes a = 10 and then commits. Question: may TXA be placed after TXB in the serialization order if TXA still read a == 0? Answer: {{c1::no}}. In the serial order TXB then TXA, TXA would have to {{c2::read a == 10}}; executions that read a == 0 are {{c3::invalid}}. <img src="paste-431146973752c2ad8b352d2de00c5a348455bc0d.jpg"><br><br>May TXA be placed after TXB in the serialization order if TXA still read a == 0?
Back A transaction's local writes become visible to others only after commit. Such a read-write conflict is detected and handled by the concurrency-control mechanism. No. <br><br>In the serial order TXB then TXA, TXA would have to read a == 10; executions that read a == 0 are invalid.<br><br>A transaction's local writes become visible to others only after commit. Such a read-write conflict is detected and handled by the concurrency-control mechanism.
Tags: ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation

Note 121: ETH::2. Semester::PProg

Deck: ETH::2. Semester::PProg
Note Type: Horvath Cloze
GUID: tc>5k@V)=2
modified

Before

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Design choice strong vs. weak isolation, concerning shared state accessed by a transaction that is also accessed outside a transaction: with strong isolation the transactional guarantees still hold (yes). It is easier for porting existing code, but difficult to implement and incurs overhead. With weak isolation they do not hold (no).

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Design choice strong vs. weak isolation, concerning shared state accessed by a transaction that is also accessed outside a transaction: with strong isolation the transactional guarantees still hold (yes). It is easier for porting existing code, but difficult to implement and incurs overhead. With weak isolation they do not hold (no).

Strong isolation: transactional and non-transactional accesses are isolated against each other. Weak isolation leaves consistency to the programmer but is cheaper.

After

Front

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Design choice strong vs. weak isolation, concerning shared state accessed by a transaction that is also accessed outside a transaction:
  • With strong isolation the transactional guarantees still hold. It is easier for porting existing code, but difficult to implement and incurs overhead.
  • With weak isolation they do not hold.

Back

ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation
Design choice strong vs. weak isolation, concerning shared state accessed by a transaction that is also accessed outside a transaction:
  • With strong isolation the transactional guarantees still hold. It is easier for porting existing code, but difficult to implement and incurs overhead.
  • With weak isolation they do not hold.

Strong isolation: transactional and non-transactional accesses are isolated against each other.
Weak isolation leaves consistency to the programmer but is cheaper.
Field-by-field Comparison
Field Before After
Text Design choice strong vs. weak isolation, concerning shared state accessed by a transaction that is also accessed outside a transaction: with {{c1::strong isolation}} the transactional guarantees still hold (yes). It is {{c2::easier for porting existing code, but difficult to implement and incurs overhead}}. With {{c3::weak isolation}} they do not hold (no). Design choice strong vs. weak isolation, concerning shared state accessed by a transaction that is also accessed outside a transaction: <br><ul><li>With {{c1::strong isolation}} the transactional guarantees still hold. It is {{c2::easier for porting existing code, but difficult to implement and incurs overhead}}. </li><li>With {{c1::weak isolation}} they do not hold.</li></ul>
Extra Strong isolation: transactional and non-transactional accesses are isolated against each other. Weak isolation leaves consistency to the programmer but is cheaper. Strong isolation: transactional and non-transactional accesses are isolated against each other. <br>Weak isolation leaves consistency to the programmer but is cheaper.
Tags: ETH::2._Semester::PProg::12._Linearizability_and_TM::7._Conflicts_and_Implementation

Note 122: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: &EOudn7bc
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
An FSM pictorially shows:
  1. the set of all possible states that a system can be in
  2. how the system transitions from one state to another

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
An FSM pictorially shows:
  1. the set of all possible states that a system can be in
  2. how the system transitions from one state to another

Current

Note has been deleted

Field-by-field Comparison
Field Before After
Text An FSM pictorially shows:<br><ol><li>{{c1::the set of all possible states that a system can be in}}</li><li>{{c2::how the system transitions from one state to another}}<br></li></ol>
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 123: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: *#UndBD{e
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
A sequential lock is an asynchronous "machine"

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
A sequential lock is an asynchronous "machine"

State transitions can take place immediately in response to input.

There is nothing that synchronizes when each state transition must occur.

Current

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Field-by-field Comparison
Field Before After
Text A sequential lock is an {{c1::asynchronous}} "machine"
Extra State transitions can take place immediately in response to input.<br><br>There is nothing that synchronizes when each state transition must occur.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits

Note 124: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: AG/0U&~#@P
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
\(N\) locations require \(\log_2 N\) address bits. 

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
\(N\) locations require \(\log_2 N\) address bits. 

 log[#locations]

Current

Note has been deleted

Field-by-field Comparison
Field Before After
Text \(N\)&nbsp;locations require {{c1::\(\log_2 N\)}} address bits.&nbsp;
Extra &nbsp;log[#locations]
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

Note 125: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: AJ~67I*]U=
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)
How does a multiplexer/selector work?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)
How does a multiplexer/selector work?

Selects one of the \(N\) inputs to connect it to the output, based on the value of a \(\log_2 N\)-bit control input called select.

Example: 2-to-1 MUX


Current

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Field-by-field Comparison
Field Before After
Front How does a multiplexer/selector work?
Back <div>Selects one of the&nbsp;\(N\)&nbsp;inputs to connect it to the output, based on the value of a&nbsp;\(\log_2 N\)-bit control input called select.</div><div><br></div><div>Example: 2-to-1 MUX</div><div><br></div><div><img src="paste-8208411dc677e909d56e87886f8feebb89586c22.jpg"><br></div>
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)

Note 126: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: AOh7q@y=Z&
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
A flip-flop is called an edge-triggered state element because it captures data on the clock edge.

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
A flip-flop is called an edge-triggered state element because it captures data on the clock edge.

A latch is a level-triggered state element.

Current

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Field-by-field Comparison
Field Before After
Text A flip-flop is called an {{c1::edge-triggered state element}} because it captures data on the clock edge.
Extra A latch is a level-triggered state element.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 127: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: B8FT@NiVSO
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters
Pros and cons of Dynamic RAM (DRAM)
  • Cheap (one bit costs only one transistor plus one capacitor)
  • Slower, reading destroys content (refresh), needs special process for manufacturing

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters
Pros and cons of Dynamic RAM (DRAM)
  • Cheap (one bit costs only one transistor plus one capacitor)
  • Slower, reading destroys content (refresh), needs special process for manufacturing

Current

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Field-by-field Comparison
Field Before After
Text Pros and cons of Dynamic RAM (DRAM)<ul><li>{{c1::Cheap (one bit costs only one transistor plus one capacitor)}}</li><li>{{c2::Slower, reading destroys content (refresh), needs special process&nbsp;for manufacturing}}</li></ul>
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters

Note 128: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: Bkh_O*c@~J
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates


If both networks are OFF at the same time, the output is floating → undefined.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates


If both networks are OFF at the same time, the output is floating → undefined.

Current

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Field-by-field Comparison
Field Before After
Text <img src="paste-a3eb18d4f8b16544780bf296d94ae3cb0386642d.jpg"><br><br> <div>If both networks are OFF at the same time, {{c1::the output is <strong>floating</strong> → undefined}}.</div>
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 129: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: BvCgV;{r@Y
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
A clock is a general mechanism that triggers transition from one state to another in a (synchronous) sequential circuit.

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
A clock is a general mechanism that triggers transition from one state to another in a (synchronous) sequential circuit.

Current

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Field-by-field Comparison
Field Before After
Text A {{c1::clock}} is a general mechanism that triggers transition from one state to another in a (synchronous) sequential circuit.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits

Note 130: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: B}b_Cs$Q2`
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
The duality property states that we can swap OR and AND, 1 and 0 in an equation and it still is true.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
The duality property states that we can swap OR and AND, 1 and 0 in an equation and it still is true.

\(\overline{(AB)} = \overline{A} + \overline{B} \) gives \(\overline{(A + B)} = \overline{A} \overline{B}\)

Current

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Field-by-field Comparison
Field Before After
Text The duality property states that {{c1:: we can swap OR and AND, 1 and 0}} in an equation and it still is true.
Extra \(\overline{(AB)} = \overline{A} + \overline{B} \)&nbsp;gives&nbsp;\(\overline{(A + B)} = \overline{A} \overline{B}\)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations

Note 131: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: C#j%f~ZG_/
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What's static power consumption?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What's static power consumption?

Power used when signals do not change.

Current

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Field-by-field Comparison
Field Before After
Front What's static power consumption?
Back Power used when signals do not change.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 132: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: C=t{~$lGP^
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What is this?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What is this?


A NOT gate/inverter.



The bubble indicates inversion.

Current

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Field-by-field Comparison
Field Before After
Front What is this?<br><br><img src="paste-ac931ff5d7f389ff58099975d1f3a0ad8ab4c537.jpg">
Back A NOT gate/inverter.<br><br><img src="paste-0ad43f42d4ff2676978fd7a8c28ab976a068e58b.jpg"><br><br>The bubble indicates inversion.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 133: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: D[owgbdJ
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::14._Register
What is this?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::14._Register
What is this?


Here we have a register.
  • It's a structure that stores more than one bit and can be read from and written to.
  • Note that there is a single WE signal for all latches for simultaneous writes.
  • This register holds 4 bits, and its data is referenced as Q[3:0].

Current

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Field-by-field Comparison
Field Before After
Front What is this?<br><br><img src="paste-be78c3f8e3954dfc7609bb2b8a3310972620f5c8.jpg">
Back Here we have a <b>register.</b><br><ul><li>It's a structure that stores more than one bit and can be read from and written to.</li><li>Note that there is a single WE signal for all latches for simultaneous writes.</li><li>This register holds 4 bits, and its data is referenced as Q[3:0].</li></ul>
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::14._Register

Note 134: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: GIu2UZfi4!
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
What does the "functional" in functional specification signify?
  1. Unique mapping from input values to output values
  2. The same input values produce the same output value every time.
  3. No memory (output does not depend on past input values)

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
What does the "functional" in functional specification signify?
  1. Unique mapping from input values to output values
  2. The same input values produce the same output value every time.
  3. No memory (output does not depend on past input values)

Example: Full 1-bit adder

Current

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Field-by-field Comparison
Field Before After
Text What does the "functional" in functional specification signify?<br><ol><li>{{c1::Unique mapping from input values to output values}}<br></li><li>{{c1::The same input values produce the same output value every time.}}<br></li><li>{{c1::No memory (output does not depend on past input values)}}<br></li></ol>
Extra Example: Full 1-bit adder<br><br><img src="paste-b9d2e36783cfe71ff832f7489428344e8584afc2.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations

Note 135: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: GJkgZHl?j0
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits
Combinational Logic, as opposed to Sequential Logic, is memoryless.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits
Combinational Logic, as opposed to Sequential Logic, is memoryless.

Outputs are strictly dependent on the combination of input values that are being applied to circuit right now.

Current

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Field-by-field Comparison
Field Before After
Text Combinational Logic, as opposed to Sequential Logic, is {{c1::memoryless}}.
Extra Outputs are strictly dependent on the combination of input values that are being applied to circuit <i>right now</i>.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits

Note 136: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: GT1cT:#V..
deleted

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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters
Pros and cons of Static RAM (SRAM)
  • Relatively fast
  • Expensive (one bit costs 6+ transistors)

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters
Pros and cons of Static RAM (SRAM)
  • Relatively fast
  • Expensive (one bit costs 6+ transistors)

Current

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Field-by-field Comparison
Field Before After
Text Pros and cons of Static RAM (SRAM)<br><ul><li>{{c1::Relatively fast}}</li><li>{{c2::Expensive (one bit costs 6+ transistors)}}</li></ul>
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters

Note 137: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: GW`le=_OwA
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::03._Logical_Completeness
Any logic function we wish to implement could be accomplished with a PLA.

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::03._Logical_Completeness
Any logic function we wish to implement could be accomplished with a PLA.

PLA consists of only AND gates, OR gates, and inverters.

We just have to program connections based on SOP of the intended logic function.

Current

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Field-by-field Comparison
Field Before After
Text {{c1::Any::Quantity?}} logic function we wish to implement could be accomplished with a PLA.
Extra PLA consists of only AND gates, OR gates, and inverters.<br><br>We just have to program connections based on SOP of the intended logic function.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::03._Logical_Completeness

Note 138: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: G]my!kE8:8
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits
A logic circuit is composed of:
  1. Inputs
  2. Outputs
  3. Functional specification
  4. Timing specification

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits
A logic circuit is composed of:
  1. Inputs
  2. Outputs
  3. Functional specification
  4. Timing specification

Current

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Field-by-field Comparison
Field Before After
Text A logic circuit is composed of:<br><ol><li>{{c1::Inputs}}</li><li>{{c1::Outputs}}</li><li>{{c2::Functional specification}}</li><li>{{c3::Timing specification}}</li></ol>
Extra <img src="paste-92c3c73e08e660520d9f65d0f54f42a8bf80bc71.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits

Note 139: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: GouO^Q1^%L
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
How can the number of a certain minterm be determined without counting lines?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
How can the number of a certain minterm be determined without counting lines?

Current

Note has been deleted

Field-by-field Comparison
Field Before After
Front How can the number of a certain minterm be determined without counting lines?
Back <img src="paste-c687a7cf6e844ba5e3892dff413f47956b4cdd9e.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit

Note 140: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: GqtZXys=xR
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
We construct basic logical units out of individual MOS transistors.

These logical units are called logic gates.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
We construct basic logical units out of individual MOS transistors.

These logical units are called logic gates.

They implement simple Boolean functions.

Current

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Field-by-field Comparison
Field Before After
Text We construct basic logical units out of individual MOS transistors. <br><br>These logical units are called {{c1::logic gates}}.
Extra They implement simple Boolean functions.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 141: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: H*(W2@+xH+
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
Which type of MOS transistor is this?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
Which type of MOS transistor is this?


n-type

Current

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Field-by-field Comparison
Field Before After
Front Which type of MOS transistor is this?<br><br><img src="paste-7d05867b68f61a963efe3a0b6c769cddefc12b2f.jpg">
Back n-type
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors

Note 142: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Occlusio
GUID: HIk47Ngez+
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
How can we select an address to read?
image-occlusion:rect:left=.0089:top=.5477:width=.2313:height=.092
image-occlusion:rect:left=.0059:top=.8424:width=.7046:height=.1459

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
How can we select an address to read?
image-occlusion:rect:left=.0089:top=.5477:width=.2313:height=.092
image-occlusion:rect:left=.0059:top=.8424:width=.7046:height=.1459

Current

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Field-by-field Comparison
Field Before After
Occlusion {{c1::image-occlusion:rect:left=.0089:top=.5477:width=.2313:height=.092}}<br>{{c2::image-occlusion:rect:left=.0059:top=.8424:width=.7046:height=.1459}}<br>
Image <img src="paste-cd3e2c310623833536d291253844967607e468c8.jpg">
Header How can we select an address to read?
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

Note 143: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: I4o5RfJsK*
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
How can we build NAND from OR and NOT?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
How can we build NAND from OR and NOT?

NAND is equivalent to OR with inputs complemented.

\(B=\overline{(XY)}=\overline X + \overline Y\)

Current

Note has been deleted

Field-by-field Comparison
Field Before After
Front How can we build NAND from OR and NOT?
Back NAND is equivalent to OR with inputs complemented.<br><br>\(B=\overline{(XY)}=\overline X + \overline Y\)<br><br><img src="paste-7f18a7c0dd30adae86b576c7e3bd558fb91d3c4b.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations

Note 144: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: IC[#R`$GWE
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What does this circuit do?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What does this circuit do?


This is the CMOS NOT Gate.

Why do we call it NOT?
  • If A = 0V then Y = 3V
  • If A = 3V then Y = 0V

Current

Note has been deleted

Field-by-field Comparison
Field Before After
Front What does this circuit do?<br><br><img src="paste-1ea8562646d826a66676f32131724f1287dda84a.jpg">
Back This is the CMOS NOT Gate.<br><br>Why do we call it NOT?<br><ul><li>If A = 0V then Y = 3V</li><li>If A = 3V then Y = 0V</li></ul>
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 145: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: IjnwO_e62-
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters
Pros and Cons of Latches and Flip-Flops:
  • Very fast, parallel access
  • Very expensive (one bit costs tens of transistors)

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters
Pros and Cons of Latches and Flip-Flops:
  • Very fast, parallel access
  • Very expensive (one bit costs tens of transistors)

Current

Note has been deleted

Field-by-field Comparison
Field Before After
Text Pros and Cons of Latches and Flip-Flops:<br><ul><li>{{c1::Very fast, parallel access}}</li><li>{{c2::Very expensive (one bit costs tens of transistors)}}</li></ul>
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters

Note 146: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: Isdz`E|.1(
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Which gate is this?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Which gate is this?


XNOR

Current

Note has been deleted

Field-by-field Comparison
Field Before After
Front Which gate is this?<br><br><img src="paste-09155718b2466228b1738f667e96bcb1c72971dd.jpg">
Back XNOR<br><br><img src="paste-262457139ca95f4bd8cd623aa4e060bfe53567df.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 147: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: I{vdVAqb$e
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::03._What_is_an_FPGA
What does FPGA stand for?

Back

ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::03._What_is_an_FPGA
What does FPGA stand for?

Field Programmable Gate Array

Current

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Field-by-field Comparison
Field Before After
Front What does FPGA stand for?
Back Field Programmable Gate Array
Tags: ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::03._What_is_an_FPGA

Note 148: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: J!BC_~c^Tq
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
On the p-type transistor, the circuit is closed when the gate is supplied with 0V.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
On the p-type transistor, the circuit is closed when the gate is supplied with 0V.

Current

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Field-by-field Comparison
Field Before After
Text On the p-type transistor, the circuit is closed when the gate is supplied with {{c1::0V}}.
Extra <img src="paste-283d91233870ed31439a32297a5e66d269bfc534.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors

Note 149: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: J!Fb=eJD*B
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
Addressability?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
Addressability?


3-bits

Current

Note has been deleted

Field-by-field Comparison
Field Before After
Front Addressability?<br><br><img src="paste-adeed554f607d7f9c2ae3a806f83b02c89cef624.jpg">
Back 3-bits
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

Note 150: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: J$BvIDQ[e=
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
If the gate of an n-type transistor is supplied with a high voltage, the connection from source to drain acts like a piece of wire (i.e., the circuit is closed).

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
If the gate of an n-type transistor is supplied with a high voltage, the connection from source to drain acts like a piece of wire (i.e., the circuit is closed).

Depending on the technology, high voltage can range from 0.3V to 3V.

Current

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Field-by-field Comparison
Field Before After
Text If the gate of an n-type transistor is supplied with {{c1::a high}} voltage, the connection from source to drain acts like {{c2::a piece of wire (i.e., the circuit is closed)}}.
Extra Depending on the technology, high voltage can range from 0.3V to 3V.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors

Note 151: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: JWeqr#]4c
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
How can we convert from the Minterm expansion of \(F\) to the Maxterm expansion of \(\overline F\)?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
How can we convert from the Minterm expansion of \(F\) to the Maxterm expansion of \(\overline F\)?

Rewrite in Maxterm form, using the same indices as \(F\).
\[\begin{array}{r l c r l} \text{E.g., } F(A,B,C) & = \sum m(3,4,5,6,7) & \longrightarrow & \overline{F}(A,B,C) & = \prod M(3,4,5,6,7) \\ & = \prod M(0,1,2) & \longrightarrow & & = \sum m(0,1,2) \end{array}\]

Current

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Field-by-field Comparison
Field Before After
Front How can we convert from the Minterm expansion of&nbsp;\(F\)&nbsp;to the Maxterm expansion of&nbsp;\(\overline F\)?
Back Rewrite in Maxterm form, using the same indices as&nbsp;\(F\).<br>\[\begin{array}{r l c r l} \text{E.g., } F(A,B,C) &amp; = \sum m(3,4,5,6,7) &amp; \longrightarrow &amp; \overline{F}(A,B,C) &amp; = \prod M(3,4,5,6,7) \\ &amp; = \prod M(0,1,2) &amp; \longrightarrow &amp; &amp; = \sum m(0,1,2) \end{array}\]<br>
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit

Note 152: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: J}Cp1R>RJL
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::16._Aside:_Implementing_Logic_Functions_Using_Memory
What is this functionally?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::16._Aside:_Implementing_Logic_Functions_Using_Memory
What is this functionally?


A memory-based lookup table.

Current

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Field-by-field Comparison
Field Before After
Front What is this functionally?<br><br><img src="paste-da1444290ceb76a444f3cae190bb00d91cbf15ff.jpg">
Back A memory-based lookup table.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::16._Aside:_Implementing_Logic_Functions_Using_Memory

Note 153: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: KEEa>PCXE`
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What's the formula for energy consumption?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What's the formula for energy consumption?

Power * Time

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Front What's the formula for energy consumption?
Back Power * Time
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 154: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
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GUID: L)2IfSjkLM
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
On the n-type transistor, the circuit is closed when the gate is supplied with 3V.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
On the n-type transistor, the circuit is closed when the gate is supplied with 3V.

Current

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Field-by-field Comparison
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Text On the n-type transistor, the circuit is closed when the gate is supplied with {{c1::3V}}.
Extra <img src="paste-58a159d5191f269f58343aa3187998262875b89e.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors

Note 155: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: Lk!m/FJd3!
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
How can we convert from Maxterm to Minterm?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
How can we convert from Maxterm to Minterm?

  1. Rewrite maxterm shorthand using minterm shorthand
  2. Replace maxterm indices with the indices not already used
E.g., \(F(A,B,C) = \prod M(0,1,2) = \sum m(3,4,5,6,7)\)

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Field-by-field Comparison
Field Before After
Front How can we convert from Maxterm to Minterm?
Back <ol><li>Rewrite maxterm shorthand using minterm shorthand</li><li>Replace maxterm indices with the indices not already used<br></li></ol>E.g.,&nbsp;\(F(A,B,C) = \prod M(0,1,2) = \sum m(3,4,5,6,7)\)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit

Note 156: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: Lyr2I#>S6v
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::1._Decoder
Decoders can be combined with OR gates to build logic functions.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::1._Decoder
Decoders can be combined with OR gates to build logic functions.

Current

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Field Before After
Text Decoders can be combined with {{c1::OR gates}} to build logic functions.
Extra <img src="paste-4b9926a6c0a612f21c80818ed3d3a9b2c1965b52.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::1._Decoder

Note 157: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: MH2*~,1ehe
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\(X \bullet Y + X \bullet \overline{Y} = X\)

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\(X \bullet Y + X \bullet \overline{Y} = X\)

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Field Before After
Text \(X \bullet Y + X \bullet \overline{Y} = {{c1::X}}\)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations

Note 158: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: MWmGMTiH]o
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
What is an implicant?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
What is an implicant?

A product (AND) of literals.

\((A \cdot B \cdot \overline{C}) \text{ , } (\overline{A} \cdot C) \text{ , } (B \cdot \overline{C})\)

Current

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Field-by-field Comparison
Field Before After
Front What is an implicant?
Back A product (AND) of literals.<br><br>\((A \cdot B \cdot \overline{C}) \text{ , } (\overline{A} \cdot C) \text{ , } (B \cdot \overline{C})\)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit

Note 159: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: MZTQ<6vlZH
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
What do the X's here mean?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
What do the X's here mean?


X (Don't Care) means I don't care what the value of this input is.

Current

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Field Before After
Front What do the X's here mean?<br><br><img src="paste-9e8019103c346073b358f3b23b79416178cdc519.jpg">
Back X (Don't Care) means I don't care what the value of this input is.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules

Note 160: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: M{Tz&Xi?.~
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
Every unique location in memory is indexed with a unique address

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
Every unique location in memory is indexed with a unique address

4 locations require 2 address bits (log[#locations]).

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Field-by-field Comparison
Field Before After
Text Every unique location in memory is indexed with a unique {{c1::address}}.&nbsp;
Extra 4 locations require 2 address bits (log[#locations]).
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

Note 161: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: N*9Rha0FR,
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
Each FSM consists of three separate parts:
  1. next state logic
  2. state register
  3. output logic

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
Each FSM consists of three separate parts:
  1. next state logic
  2. state register
  3. output logic



At the beginning of the clock cycle, next state is latched into the state register

Current

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Field-by-field Comparison
Field Before After
Text Each FSM consists of three separate parts:<br><ol><li>{{c1::next state logic}}</li><li>{{c2::state register}}</li><li>{{c3::output logic}}</li></ol>
Extra <img src="paste-f282a35cb1ef5e0d4f8f098548b2bdb621bdf0da.jpg"><br><br>At the beginning of the clock cycle, next state is latched into the state register
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 162: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: NO,[UqkjjY
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
Address space size?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
Address space size?


2 (total of 6 bits)

Current

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Field-by-field Comparison
Field Before After
Front Address space size?<br><br><img src="paste-adeed554f607d7f9c2ae3a806f83b02c89cef624.jpg">
Back 2 (total of 6 bits)
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

Note 163: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: Nr/WO;(0{4
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)
Multiplexers can be used as "lookup tables" to perform logic functions.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)
Multiplexers can be used as "lookup tables" to perform logic functions.

Current

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Field Before After
Text Multiplexers can be used as {{c1::"lookup tables" to perform logic functions}}.
Extra <img src="paste-a0643b754113ab32abc6e5adfed855ac37f050e3.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)

Note 164: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: P2t5@m8Q~.
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What gate is this?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What gate is this?


This is the CMOS AND Gate.

Current

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Field-by-field Comparison
Field Before After
Front What gate is this?<br><br><img src="paste-2ad6d40fa1eb42fa0ccdeb5a2af1449399f4157c.jpg">
Back This is the CMOS AND Gate.<br><br><img src="paste-3ec26993d5dc59b7a394208bdd22963894227581.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 165: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: P938wRh{~H
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
Which properties do we need to implement a state register?
  1. We need to store data at the beginning of every clock cycle
  2. The data must be available during the entire clock cycle

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
Which properties do we need to implement a state register?
  1. We need to store data at the beginning of every clock cycle
  2. The data must be available during the entire clock cycle


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Field-by-field Comparison
Field Before After
Text Which properties do we need to implement a state register?<br><ol><li>{{c1::We need to store data at the beginning of every clock cycle}}<br></li><li>{{c2::The data must be available during the entire clock cycle}}<br></li></ol>
Extra <img src="paste-d15605117cc9664c84a7753d40f0a3d09f3febbd.jpg"><br><img src="paste-f6afd0db6d1e758d9b809052a6b2ad201b0950b0.jpg">
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 166: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: PMc1ViG{^J
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
Most modern computers are synchronous "machines".

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
Most modern computers are synchronous "machines".

State transitions take place at fixed units of time (i.e., potentially delayed response to input, synchronized to an external signal).

Controlled in part by a clock, as we will see soon.

Current

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Field Before After
Text Most modern computers are {{c1::synchronous}} "machines".
Extra State transitions take place at fixed units of time (i.e., potentially delayed response to input, synchronized to an external signal).<br><br>Controlled in part by a clock, as we will see soon.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits

Note 167: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: Q+Ol+3O^DB
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Series connections are slower than parallel connections.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Series connections are slower than parallel connections.

More resistance on the wire.

Current

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Field Before After
Text Series connections are {{c1::slower::Speed}} than parallel connections.
Extra More resistance on the wire.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 168: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: QSB?1}FgZ9
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
p-type transistors are good at pulling up the voltage.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
p-type transistors are good at pulling up the voltage.

Current

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Field-by-field Comparison
Field Before After
Text <b>p</b>-type transistors are good at pulling {{c1::u<b>p</b>}}&nbsp;the voltage.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 169: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Occlusio
GUID: [,YWN{Lwu
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic PlsFix::DELETE
What is this?

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic PlsFix::DELETE
What is this?

Current

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Image <img src="paste-6a8326151aeedf40c81bab85eb67ee61a0bfdc28.jpg">
Header What is this?
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic PlsFix::DELETE

Note 170: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: b]5EOR.;[y
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
What is a Finite State Machine (FSM)?

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
What is a Finite State Machine (FSM)?

A discrete-time model of a stateful system.

Each state represents a snapshot of the system at a given time.

Current

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Field-by-field Comparison
Field Before After
Front What is a Finite State Machine (FSM)?
Back A discrete-time model of a stateful system.<br><br>Each state represents a snapshot of the system at a given time.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 171: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: c.C#J,&->z
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic
What is the non-greyed out part of the circuit?

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic
What is the non-greyed out part of the circuit?


Output logic and outputs.

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Field Before After
Front What is the non-greyed out part of the circuit?<br><br><img src="paste-e862550d817fcb452eefec1d1adda5fe368464f1.jpg">
Back Output logic and outputs.<br><br><img src="paste-cd6ef59f2ccfee5f7ab46a1cdc992280c12a7ba5.jpg">
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic

Note 172: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: c>-yp[Ry[S
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
How can we make an AND gate?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
How can we make an AND gate?

We make an AND gate using one NAND gate and one NOT gate:

Current

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Field-by-field Comparison
Field Before After
Front How can we make an AND gate?
Back We make an AND gate using one NAND gate and one NOT gate:<br><br><img src="paste-0596c472398ba477eff721024a309ad41e750430.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 173: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Occlusio
GUID: cK)3)DLM_o
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::01._Full_Adder
Full Adder
image-occlusion:rect:left=.8168:top=.9307:width=.1774:height=.0558:oi=1

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::01._Full_Adder
Full Adder
image-occlusion:rect:left=.8168:top=.9307:width=.1774:height=.0558:oi=1

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Field Before After
Occlusion {{c1::image-occlusion:rect:left=.8168:top=.9307:width=.1774:height=.0558:oi=1}}<br>
Image <img src="paste-8436c8f8af1bf260ebd78993c1d11a17c97c0dd2.jpg">
Header Full Adder
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::01._Full_Adder

Note 174: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: cRGP4XGmZM
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
Product of Sums is equivalent to CNF.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
Product of Sums is equivalent to CNF.

This is also the DeMorgan of SOP of \(\overline F\).

Current

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Field-by-field Comparison
Field Before After
Text Product of Sums is equivalent to {{c1::CNF}}.
Extra This is also the DeMorgan of SOP of&nbsp;\(\overline F\).
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit

Note 175: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: e.w!.^HZQk
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::04._Comparator
What is this?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::04._Comparator
What is this?


An equality checker.

Current

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Field-by-field Comparison
Field Before After
Front What is this?<br><br><img src="paste-9ee9299a0aa47519e61e8ffe9cefcd2d2ffa51c2.jpg">
Back An equality checker.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::04._Comparator

Note 176: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: e1dy/}l($w
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What does this circuit do?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What does this circuit do?


It's the CMOS NAND Gate.


  • P1 and P2 are in parallel; only one must be ON to pull up the output to 3V.
  • N1 and N2 are connected in series; both must be ON to pull down the output to 0V.

Current

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Field-by-field Comparison
Field Before After
Front What does this circuit do?<br><br><img src="paste-bccbffeadc7963887cae6412e8d018f79008f8a4.jpg">
Back It's the CMOS NAND Gate.<br><br><img src="paste-cc6b665cdbfe3838f2f72c3f5c383b6787057523.jpg"><br><div><ul><li>P1 and P2 are <b>in parallel</b>; only one must be ON to pull up the output to 3V.</li><li>N1 and N2 are connected <b>in series</b>; both must be ON to pull down the output to 0V.</li></ul></div>
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 177: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: eh2^a;u=sR
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
How can we convert the expansion of \(F\) to the expansion of \(\overline F\)?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
How can we convert the expansion of \(F\) to the expansion of \(\overline F\)?

\[\begin{array}{r l c r l} \text{E.g., } F(A,B,C) & = \sum m(3,4,5,6,7) & \longrightarrow & \overline{F}(A,B,C) & = \sum m(0,1,2) \\ & = \prod M(0,1,2) & \longrightarrow & & = \prod M(3,4,5,6,7) \end{array}\]

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Field-by-field Comparison
Field Before After
Front How can we convert the expansion of&nbsp;\(F\)&nbsp;to the expansion of&nbsp;\(\overline F\)?
Back \[\begin{array}{r l c r l} \text{E.g., } F(A,B,C) &amp; = \sum m(3,4,5,6,7) &amp; \longrightarrow &amp; \overline{F}(A,B,C) &amp; = \sum m(0,1,2) \\ &amp; = \prod M(0,1,2) &amp; \longrightarrow &amp; &amp; = \prod M(3,4,5,6,7) \end{array}\]<br>
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit

Note 178: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: fj@3y5gt5P
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
The state of a system is a snapshot of all relevant elements of the system at the moment of the snapshot.

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
The state of a system is a snapshot of all relevant elements of the system at the moment of the snapshot.

Current

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Field-by-field Comparison
Field Before After
Text The {{c1::state}} of a system is a snapshot of all relevant elements of the system at the moment of the snapshot.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits

Note 179: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Occlusio
GUID: g(oknS2XIO
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::03._Finite_State_Machine:_State_Transition_Table
Determine the SOP of \(S_1'\) from this state transition table:
image-occlusion:rect:left=.1192:top=.7777:width=.5322:height=.0901:oi=1

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::03._Finite_State_Machine:_State_Transition_Table
Determine the SOP of \(S_1'\) from this state transition table:
image-occlusion:rect:left=.1192:top=.7777:width=.5322:height=.0901:oi=1

Current

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Field-by-field Comparison
Field Before After
Occlusion {{c1::image-occlusion:rect:left=.1192:top=.7777:width=.5322:height=.0901:oi=1}}<br>
Image <img src="paste-2b0785e36a987370d617f3eeadb768dc3c9ce66d.jpg">
Header Determine the SOP of&nbsp;\(S_1'\)&nbsp;from this state transition table:
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::03._Finite_State_Machine:_State_Transition_Table

Note 180: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: g-~*^Ki!(:
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer
How do we model a BUS as a circuit?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer
How do we model a BUS as a circuit?

You can have two tri-state buffers: one driven by CPU, the other memory; and ensure at most one is enabled at any time.

Current

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Field-by-field Comparison
Field Before After
Front How do we model a BUS as a circuit?
Back You can have two tri-state buffers: one driven by CPU, the other memory; and ensure at most one is enabled at any time.<br><br><img src="paste-3e60268fdf3d3d4e9613807017fd11ee2dd4909f.jpg">
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer

Note 181: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: g.dcXCwTR^
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
How many locations and bits does this memory array have?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
How many locations and bits does this memory array have?


4 locations X 3 bits

Current

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Field-by-field Comparison
Field Before After
Front How many locations and bits does this memory array have?<br><br><img src="paste-527c14fba71cb77a30a80a0db3ff30a5ca8a1b03.jpg">
Back 4 locations X 3 bits
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

Note 182: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: g8HHZjvwjk
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::13._The_Gated_D_Latch
How do we guarantee correct operation of an R-S Latch?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::13._The_Gated_D_Latch
How do we guarantee correct operation of an R-S Latch?

We add two more NAND gates.



\(Q\) takes the value of \(D\), when write enable (WE) is set to 1.
\(S\) and \(R\) can never be 0 at the same time!

Current

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Field-by-field Comparison
Field Before After
Front How do we guarantee correct operation of an R-S Latch?
Back We add two more NAND gates.<br><br><img src="paste-75ed2b046c6dd5698e1016b588d9baa5ff3affdf.jpg"><br><br>\(Q\)&nbsp;takes the value of&nbsp;\(D\), when write enable (WE) is set to 1.<br>\(S\)&nbsp;and&nbsp;\(R\)&nbsp;can never be 0 at the same time!<br><br><img src="paste-d6a38ff36eeae6a05033cd1da3fa1f32da25717f.jpg">
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::13._The_Gated_D_Latch

Note 183: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: g<38ETccf&
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
Combinational logic evaluates for the length of the clock cycle.

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
Combinational logic evaluates for the length of the clock cycle.

Current

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Field-by-field Comparison
Field Before After
Text Combinational logic evaluates for the {{c1::length}} of the clock cycle.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits

Note 184: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: h!H8&>iQx{
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::02._The_Programmable_Logic_Array_(PLA)
How do we determine the number of OR gates in a PLA? 

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::02._The_Programmable_Logic_Array_(PLA)
How do we determine the number of OR gates in a PLA? 

The number of output columns in the truth table.

Current

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Field-by-field Comparison
Field Before After
Front How do we determine the number of OR gates in a PLA?&nbsp;
Back The number of output columns in the truth table.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::02._The_Programmable_Logic_Array_(PLA)

Note 185: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: hQ)3[a]Xq<
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What gates is this?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What gates is this?


The CMOS NAND Gate.

Current

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Field-by-field Comparison
Field Before After
Front What gates is this?<br><br><img src="paste-b6777165efef100cab46f26906ce60b1d5d3a866.jpg">
Back The CMOS NAND Gate.<br><br><img src="paste-953f00465848000258867b4eb3678f8b985d22d1.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 186: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: iyge$&[U#_
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
What is this?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
What is this?


A priority circuit.
  • Inputs: "Requestors" with priority levels
  • Outputs: "Grant" signal for each requestor

Current

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Field-by-field Comparison
Field Before After
Front What is this?<br><br><img src="paste-50fbc0b6a9081d2f896cc292f56cc4a470bd44ab.jpg">
Back A priority circuit.<br><ul><li>Inputs: "Requestors" with priority levels</li><li>Outputs: "Grant" signal for each requestor</li></ul>
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules

Note 187: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: jY?vAb-}P$
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters
Pros and cons of other storage technology (flash memory, hard disk, tape)
  • Very cheap
  • Much slower, access takes a long time, non-volatile

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters
Pros and cons of other storage technology (flash memory, hard disk, tape)
  • Very cheap
  • Much slower, access takes a long time, non-volatile

Current

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Field-by-field Comparison
Field Before After
Text Pros and cons of other storage technology (flash memory, hard disk, tape)<br><ul><li>{{c1::Very cheap}}</li><li>{{c2::Much slower, access takes a long time, non-volatile}}</li></ul>
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters

Note 188: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: jgnr@Obi8f
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
Two types of finite state machines differ in the output logic:
  1. Moore FSM: outputs depend only on the current state
  2. Mealy FSM: outputs depend on the current state and the inputs

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
Two types of finite state machines differ in the output logic:
  1. Moore FSM: outputs depend only on the current state
  2. Mealy FSM: outputs depend on the current state and the inputs

Current

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Field-by-field Comparison
Field Before After
Text Two types of finite state machines differ in the output logic:<br><ol><li>{{c1::Moore FSM}}: outputs depend only on the current state</li><li>{{c1::Mealy FSM}}: outputs depend on the current state and the inputs</li></ol>
Extra <img src="paste-8c32ce33990f4253676703e6ef1745ff9f544c8e.jpg">
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 189: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: jylgnWO`cY
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates


If both networks are ON at the same time, there is a short circuit → likely incorrect operation.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates


If both networks are ON at the same time, there is a short circuit → likely incorrect operation.

Current

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Field-by-field Comparison
Field Before After
Text <img src="paste-a3eb18d4f8b16544780bf296d94ae3cb0386642d.jpg"><br><br><div>If both networks are ON at the same time, there is {{c1::a <strong>short circuit</strong> → likely incorrect operation}}.</div>
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 190: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: kOBb
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer
What does the Z mean here?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer
What does the Z mean here?


Signal that is not driven by any circuit (e.g. open circuit, floating wire).

Current

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Field-by-field Comparison
Field Before After
Front What does the Z mean here?<br><br><img src="paste-6aad4a37bc003259212e2f00d56e604b0cf5c2b8.jpg">
Back Signal that is not driven by any circuit (e.g. open circuit, floating wire).
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer

Note 191: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: kjuyg1m}9]
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\(A+B\) signifies "A or B".

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\(A+B\) signifies "A or B".


Current

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Field-by-field Comparison
Field Before After
Text \(A+B\)&nbsp;signifies {{c1::"A or B"}}.
Extra <img src="paste-e9d93adb6e4be16c829b5ca7bc0873cb10bfaaad.jpg"><br><img src="paste-98398b7664b21c58363c0b63982187f6bc6981aa.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations

Note 192: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: km!Z
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::06._Finite_State_Machine:_State_Encoding
One-Hot Encoding:
  • Each bit encodes a different state
    • Uses num_states bits to represent the states
    • Exactly 1 bit is "hot" for a given state
  • Simplest design process – very automatable
  • Minimizes next state logic, maximizes # flip-flops

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::06._Finite_State_Machine:_State_Encoding
One-Hot Encoding:
  • Each bit encodes a different state
    • Uses num_states bits to represent the states
    • Exactly 1 bit is "hot" for a given state
  • Simplest design process – very automatable
  • Minimizes next state logic, maximizes # flip-flops

Example state encodings: 0001, 0010, 0100, 1000

Current

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Field-by-field Comparison
Field Before After
Text <div>{{c1::One-Hot Encoding}}<strong>:</strong></div> <ul> <li>Each bit {{c4::encodes a different state <ul> <li>Uses <em>num_states</em> bits to represent the states</li> <li>Exactly 1 bit is "hot" for a given state</li></ul>}}</li> <li><strong>Simplest design process</strong> – very automatable</li> <li><strong>Minimizes</strong> {{c2::next state logic}}, <strong>maximizes</strong> {{c3::# flip-flops}}</li></ul>
Extra <em>Example state encodings:</em>&nbsp;0001, 0010, 0100, 1000
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::06._Finite_State_Machine:_State_Encoding

Note 193: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: kp|/N}vt~s
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::02._The_Programmable_Logic_Array_(PLA)
How do we determine the number of AND gates in a PLA?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::02._The_Programmable_Logic_Array_(PLA)
How do we determine the number of AND gates in a PLA?

For an n-input logic function, we need a PLA with 2ⁿ n-input AND gates.

Remember SOP:
 the number of possible minterms

Current

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Field-by-field Comparison
Field Before After
Front <div><strong>How do we determine the number of AND gates in a PLA?</strong></div>
Back For an n-input logic function, we need a PLA with 2ⁿ n-input AND gates.<br><strong><br>Remember SOP:</strong>&nbsp;the number of possible minterms
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::02._The_Programmable_Logic_Array_(PLA)

Note 194: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Occlusio
GUID: l:)hd01;==
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Front

ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::06._More_about_FPGAs
What is this hidden component?
image-occlusion:rect:left=.3893:top=.0178:width=.4877:height=.0674:oi=1
image-occlusion:rect:left=.5552:top=.3107:width=.4354:height=.1021:oi=1

Back

ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::06._More_about_FPGAs
What is this hidden component?
image-occlusion:rect:left=.3893:top=.0178:width=.4877:height=.0674:oi=1
image-occlusion:rect:left=.5552:top=.3107:width=.4354:height=.1021:oi=1

Current

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Field Before After
Occlusion {{c1::image-occlusion:rect:left=.3893:top=.0178:width=.4877:height=.0674:oi=1}}<br>{{c2::image-occlusion:rect:left=.5552:top=.3107:width=.4354:height=.1021:oi=1}}<br>
Image <img src="paste-bc35d0ae17174e4109a0bc070e1da9b4d468886b.jpg">
Header What is this hidden component?
Tags: ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::06._More_about_FPGAs

Note 195: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: l:L$hWai[V
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Which gate is this?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Which gate is this?


NOR

Current

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Field-by-field Comparison
Field Before After
Front Which gate is this?<br><br><img src="paste-2ddd8398d7ccd94313aad36079863d4f5ef4cd1f.jpg">
Back NOR<br><br><img src="paste-6304f984df50a0b8281ed5bff64f29273cd05051.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 196: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: lJFlk8]f26
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
How can we build NOR from NOT and AND?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
How can we build NOR from NOT and AND?

NOR is equivalent to AND with inputs complemented.

\(A=\overline{(X+Y)}=\overline X \space\overline Y\)

Current

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Field-by-field Comparison
Field Before After
Front How can we build NOR from NOT and AND?
Back NOR is equivalent to AND with inputs complemented.<br><br>\(A=\overline{(X+Y)}=\overline X \space\overline Y\)<br><br><img src="paste-4f2a2ce8e54cf095a8c32b10eb76d836070ebd30.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations

Note 197: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: lSt^W77c/I
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
By combining:
  1. Conductors (Metal)
  2. Insulators (Oxide)
  3. Semiconductors
We get a Transistor (MOS).

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
By combining:
  1. Conductors (Metal)
  2. Insulators (Oxide)
  3. Semiconductors
We get a Transistor (MOS).

Current

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Field Before After
Text <div><strong>By combining:</strong></div> <ol><li>{{c1::Conductors (<b>M</b>etal)}}<br></li> <li>{{c2::Insulators (<strong>O</strong>xide)}}<br></li> <li>{{c3::<strong>S</strong>emiconductors}}<br></li></ol> <div><strong>We get a&nbsp;</strong>{{c4::Transistor (MOS)}}.</div>
Extra <img src="paste-f9e68afc631519419a56d36751cdb4d5779e1ac1.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors

Note 198: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: m6MCp)pX:Q
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
What is the Uniting Theorem?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
What is the Uniting Theorem?

\(F=A\overline B+AB\)

Current

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Field-by-field Comparison
Field Before After
Front What is the Uniting Theorem?
Back \(F=A\overline B+AB\)<br><br><img src="paste-544b792a3b0a0008ec05e73f83984d8d6b36adab.jpg">
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules

Note 199: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: m7qIFy%!oi
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
What is a minterm?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
What is a minterm?

A product (AND) that includes all input variables.

\((A \cdot B \cdot \overline{C}) \text{ , } (\overline{A} \cdot \overline{B} \cdot C) \text{ , } (\overline{A} \cdot B \cdot \overline{C})\)

Current

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Field-by-field Comparison
Field Before After
Front What is a minterm?
Back A product (AND) that includes all input variables.<br><br>\((A \cdot B \cdot \overline{C}) \text{ , } (\overline{A} \cdot \overline{B} \cdot C) \text{ , } (\overline{A} \cdot B \cdot \overline{C})\)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit

Note 200: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: n!oY_a%~!Q
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
If the gate of the n-type transistor is supplied with zero voltage, the connection between the source and drain is broken (i.e., the circuit is open).

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
If the gate of the n-type transistor is supplied with zero voltage, the connection between the source and drain is broken (i.e., the circuit is open).

Current

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Field-by-field Comparison
Field Before After
Text If the gate of the n-type transistor is supplied with {{c1::zero}} voltage, the connection between the source and drain is {{c2::broken (i.e., the circuit is open)}}.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors

Note 201: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: nGy?>L{vz*
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)
A 3-LUT can implement any 3-bit input function.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)
A 3-LUT can implement any 3-bit input function.

(LUT = Lookup Table)

Current

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Field-by-field Comparison
Field Before After
Text A 3-LUT can implement {{c1::any 3-bit input function}}.
Extra (LUT = Lookup Table)<br><br><img src="paste-5ef924f9dd1bae5892f2b78cbd64716dc1471cf4.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)

Note 202: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: nZ9{K+v5e:
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic
What is this?

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic
What is this?


A state register.

Current

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Field-by-field Comparison
Field Before After
Front What is this?<br><br><img src="paste-4acc4c494556bcdc7cbaf9afc6e9b6e94385de83.jpg">
Back A state register.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic

Note 203: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: nZ:%JyRTd=
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
What is Addressability?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
What is Addressability?

The number of bits of information stored in each location.

E.g. here addressability is 8 bits.

Current

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Field-by-field Comparison
Field Before After
Front What is Addressability?
Back The number of bits of information stored in each location. <br><br>E.g. here addressability is 8 bits.<br><br><img src="paste-cdfafca1398985f93cea204a6b7b7073d008729e.jpg">
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

Note 204: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: n]Q[NPQ}z>
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Modern computers use both n-type and p-type transistors, i.e. Complementary MOS (CMOS) technology.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Modern computers use both n-type and p-type transistors, i.e. Complementary MOS (CMOS) technology.

Current

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Field-by-field Comparison
Field Before After
Text Modern computers use both n-type and p-type transistors, i.e. {{c1::Complementary MOS (CMOS) technology}}.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 205: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: na4nPYvDI]
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::1._Decoder
How does a decoder work?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::1._Decoder
How does a decoder work?

  1. \(n\) possible inputs and \(2^n\) outputs
  2. Exactly one of the outputs is 1 and all the rest are 0s
  3. The output that is logically 1 is the output corresponding to the input pattern that the logic circuit is expected to detect
A decoder is an "input pattern detector".

Example: 2-to-4 decoder

Current

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Field-by-field Comparison
Field Before After
Front How does a decoder work?
Back <ol><li>\(n\) possible inputs and&nbsp;\(2^n\)&nbsp;outputs</li><li>Exactly one of the outputs is 1 and all the rest are 0s</li><li>The output that is logically 1 is the output corresponding to the input pattern that the logic circuit is expected to detect</li></ol><div>A decoder is an "input pattern detector".<br></div><div><br></div><div>Example: 2-to-4 decoder</div><div><img src="paste-41f427073aea6bbe436440d617e8ed5e4b95a46e.jpg"><br></div>
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::1._Decoder

Note 206: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: o3LWZaHF!=
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
Writing to Memory

What is \(D_i\) here?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
Writing to Memory

What is \(D_i\) here?


Input.

Current

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Field-by-field Comparison
Field Before After
Front Writing to Memory<br><br>What is&nbsp;\(D_i\)&nbsp;here?<br><br><img src="paste-7e3105fcf0e2a3f5313495e28ac3d165f96c13ac.jpg">
Back Input.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

Note 207: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: oFt2FboU]G
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\(A\bullet B\) signifies "A and B".

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\(A\bullet B\) signifies "A and B".


Current

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Field-by-field Comparison
Field Before After
Text \(A\bullet B\)&nbsp;signifies {{c1::"A and B"}}.
Extra <img src="paste-2a88f83499c002bb4aefd9f0fb723e34a306acc2.jpg"><br><img src="paste-5243b849a82a96a61d8a2a0cb57382d5d754be34.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations

Note 208: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: oJl`_}4^pa
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\(X + X \bullet Y = X\)

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\(X + X \bullet Y = X\)

Current

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Field-by-field Comparison
Field Before After
Text \(X + X \bullet Y = {{c1::X}}\)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations

Note 209: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: oO*YyBr@a8
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Deleted Note

Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
We can use D Flip-Flops to implement the state register.

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
We can use D Flip-Flops to implement the state register.

Current

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Field-by-field Comparison
Field Before After
Text We can use {{c1::D Flip-Flops}}&nbsp;to implement the state register.
Extra <img src="paste-2f7dcb7191f560d4f7710228edba5ec2380729ab.jpg">
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 210: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: oUzmIp%E`>
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What's the formula for dynamic power consumption?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What's the formula for dynamic power consumption?

\(C\cdot V^2\cdot f\)

\(C =\) capacitance of the circuit (wires and gates)
\(V =\) supply voltage
\(f =\) charging frequency of the capacitor

Current

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Field-by-field Comparison
Field Before After
Front What's the formula for dynamic power consumption?
Back \(C\cdot V^2\cdot f\)<br><br>\(C =\)&nbsp;capacitance of the circuit (wires and gates)<br>\(V =\)&nbsp;supply voltage<br>\(f =\)&nbsp;charging frequency of the capacitor
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 211: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: o`-s)9=Wl[
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)
The output C of a MUX is always connected to either the input A or the input B

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)
The output C of a MUX is always connected to either the input A or the input B

Output value depends on the value of the select line S.

Current

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Field-by-field Comparison
Field Before After
Text The output C of a MUX is always connected to {{c1::either the input A or the input B}}.&nbsp;
Extra Output value depends on the value of the select line S.<br><br><img src="paste-4208651bb851c0f85958e6a1f06734edf09d758c.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::2._Multiplexer_(MUX)

Note 212: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: p2iMO-L)D:
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
Which type of MOS transistor is this?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
Which type of MOS transistor is this?


p-type

Current

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Field-by-field Comparison
Field Before After
Front Which type of MOS transistor is this?<br><br><img src="paste-c2def2ad64ef59d3bc9ea12d95969214b321c975.jpg">
Back p-type
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors

Note 213: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: p8m/.jeCY9
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
When transistors are in series, the network is ON only if all transistors are ON.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
When transistors are in series, the network is ON only if all transistors are ON.

Current

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Field-by-field Comparison
Field Before After
Text When transistors are in series, the network is ON only if {{c1::all transistors are ON}}.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 214: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: pJ5WeT=%X,
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits
Functional specification describes the relationship between inputs and outputs.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits
Functional specification describes the relationship between inputs and outputs.

Current

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Field-by-field Comparison
Field Before After
Text Functional specification describes {{c1::the relationship between inputs and outputs}}.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits

Note 215: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: padK$?kSq8
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Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::02._The_Programmable_Logic_Array_(PLA)
How do we implement a logic function in a PLA?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::02._The_Programmable_Logic_Array_(PLA)
How do we implement a logic function in a PLA?

Connect the output of an AND gate to the input of an OR gate if the corresponding minterm is included in the SOP.

This is a simple programmable logic construct.

Current

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Field-by-field Comparison
Field Before After
Front How do we implement a logic function in a PLA?
Back Connect the output of an AND gate to the input of an OR gate if the corresponding minterm is included in the SOP.<br><br>This is a simple programmable logic construct.<br><br><img src="paste-2fbd7177ca3914ec569c4d1587320498ff0c8fa1.jpg">
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::02._The_Programmable_Logic_Array_(PLA)

Note 216: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: p}!>Qc
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Deleted Note

Front

ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::03._What_is_an_FPGA
A FPGA is a software-reconfigurable hardware substrate.

Back

ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::03._What_is_an_FPGA
A FPGA is a software-reconfigurable hardware substrate.

  • Reconfigurable functions
  • Reconfigurable interconnection of functions
  • Reconfigurable input/output (IO)

Current

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Field-by-field Comparison
Field Before After
Text A FPGA is a {{c1::software-reconfigurable hardware substrate}}.
Extra <ul><li>Reconfigurable functions</li><li>Reconfigurable interconnection of functions</li><li>Reconfigurable input/output (IO)</li></ul>
Tags: ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::03._What_is_an_FPGA

Note 217: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: q)+B1jCKdJ
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits
Timing specification describes the delay between inputs changing and outputs responding.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits
Timing specification describes the delay between inputs changing and outputs responding.

Current

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Field-by-field Comparison
Field Before After
Text Timing specification describes {{c1::the delay between inputs changing and outputs responding}}.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::3._Combinational_Logic_Circuits

Note 218: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: q)njawwNYM
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Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer
A tri-state buffer enables gating of different signals onto a wire.

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer
A tri-state buffer enables gating of different signals onto a wire.



It acts like a switch.

Current

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Field-by-field Comparison
Field Before After
Text A tri-state buffer enables {{c1::gating of different signals onto a wire}}.
Extra <img src="paste-6aad4a37bc003259212e2f00d56e604b0cf5c2b8.jpg"><br><br>It acts like a switch.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::06._Tri-State_Buffer

Note 219: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: q,=4BpC=Eo
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Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::12._Basic_Storage_Element:_The_R-S_Latch
R-S Latch
  • Data is stored at Q (inverse at Q')
  • S and R are control inputs
    • In quiescent (idle) state, both S and R are held at 1
    • S (set): drive S to 0 (keeping R at 1) to change Q to 1
    • R (reset): drive R to 0 (keeping S at 1) to change Q to 0

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::12._Basic_Storage_Element:_The_R-S_Latch
R-S Latch
  • Data is stored at Q (inverse at Q')
  • S and R are control inputs
    • In quiescent (idle) state, both S and R are held at 1
    • S (set): drive S to 0 (keeping R at 1) to change Q to 1
    • R (reset): drive R to 0 (keeping S at 1) to change Q to 0



S and R should not both be 0 at the same time.

Current

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Field-by-field Comparison
Field Before After
Text R-S Latch<br><ul><li>Data is stored at {{c1::Q (inverse at Q')}}</li><li>S and R are {{c2::control inputs}}</li><ul> <li>In quiescent (idle) state, {{c3::both S and R are held at 1}}</li><li>S (set): {{c4::drive S to 0 (keeping R at 1) to change Q to 1}}</li><li>R (reset): {{c4::drive R to 0 (keeping S at 1) to change Q to 0}}</li></ul></ul>
Extra <img src="paste-d484990009a33988ad2d3a060d667ec92928c41c.jpg"><br><br>S and R should not both be 0 at the same time.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::12._Basic_Storage_Element:_The_R-S_Latch

Note 220: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: q1yvsXE,ua
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Which gate is this?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Which gate is this?


XOR

Current

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Field-by-field Comparison
Field Before After
Front Which gate is this?<br><br><img src="paste-7d4535880d22382faf2a469bb62f36d71ac1ecd9.jpg">
Back XOR<br><br><img src="paste-fbcccd66f0a26a44febf8dcce68a686e6461715e.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 221: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: qks
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::03._Logical_Completeness
The set of gates {AND, OR, NOT} is logically complete because we can build a circuit to carry out the specification of any truth table we wish, without using any other kind of gate.

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::03._Logical_Completeness
The set of gates {AND, OR, NOT} is logically complete because we can build a circuit to carry out the specification of any truth table we wish, without using any other kind of gate.

Current

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Field-by-field Comparison
Field Before After
Text The set of gates {AND, OR, NOT} is {{c1::logically complete}} because we can build a circuit to carry out the specification of any truth table we wish, without using any other kind of gate.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::03._Logical_Completeness

Note 222: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: qq
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\(\overline A\) signifies "not A".

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\(\overline A\) signifies "not A".


Current

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Field-by-field Comparison
Field Before After
Text \(\overline A\)&nbsp;signifies {{c1::"not A"}}.
Extra <img src="paste-d885cebb297fd9ce2e11b004403626df910ecefb.jpg"><br><img src="paste-276f415400a598a88e43cf6a665f2766498f5ec1.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations

Note 223: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: rJHb8Hi/z_
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
Sum of Products Form is equivalent to DNF/minterm expansion.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
Sum of Products Form is equivalent to DNF/minterm expansion.

Current

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Field-by-field Comparison
Field Before After
Text Sum of Products Form is equivalent to {{c1::DNF/minterm expansion}}.
Extra <img src="paste-49bc2215747c5b28dbf9a8675f61e9ebdb61648d.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit

Note 224: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: rKhGk@]2@!
deleted

Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What is dynamic power consumption?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What is dynamic power consumption?

Power used to charge capacitance as signals change (0\(\iff\)1).

Current

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Field-by-field Comparison
Field Before After
Front What is dynamic power consumption?
Back Power used to charge capacitance as signals change (0\(\iff\)1).
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 225: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: rUfqRU)=~O
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Deleted Note

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\((X + \overline{Y}) \bullet Y = X \bullet Y\)

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations
\((X + \overline{Y}) \bullet Y = X \bullet Y\)

Current

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Field-by-field Comparison
Field Before After
Text \((X + \overline{Y}) \bullet Y ={{c1:: X \bullet Y}}\)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::4._Boolean_Logic_Equations

Note 226: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: rnH{-|yj$G
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
A clock synchronizes state changes across many sequential circuit elements.

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
A clock synchronizes state changes across many sequential circuit elements.

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Text A clock {{c1::synchronizes state changes}} across many sequential circuit elements.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits

Note 227: ETH::2. Semester::DDCA

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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
What are the two types of MOS transistors?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors
What are the two types of MOS transistors?

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Front What are the two types of MOS transistors?
Back <img src="paste-38750c04faf9612e70d859133acd28c824b5e12a.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::1._Transistors

Note 228: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
What is a maxterm?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
What is a maxterm?

A sum (OR) that includes all input variables.

\((A + \overline{B} + \overline{C}) \text{ , } (\overline{A} + B + \overline{C}) \text{ , } (A + B + \overline{C})\)

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Front What is a maxterm?
Back A&nbsp;sum (OR) that includes all input variables.<br><br>\((A + \overline{B} + \overline{C}) \text{ , } (\overline{A} + B + \overline{C}) \text{ , } (A + B + \overline{C})\)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit

Note 229: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::06._More_about_FPGAs
What are the two main building blocks of FPGAs?

Back

ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::06._More_about_FPGAs
What are the two main building blocks of FPGAs?

Look-Up Tables (LUT) and Switches.

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Front What are the two main building blocks of FPGAs?
Back Look-Up Tables (LUT) and Switches.<br><br><img src="paste-cee6c807e9f899a8a1405b26996492bb8e767dc2.jpg">
Tags: ETH::2._Semester::DDCA::04b._Introduction_to_the_Labs_and_FPGAs::06._More_about_FPGAs

Note 230: ETH::2. Semester::DDCA

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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic
What is the non-greyed out part of the circuit?

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic
What is the non-greyed out part of the circuit?


Inputs and next state logic.

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Front What is the non-greyed out part of the circuit?<br><br><img src="paste-85e71c9bf7ed1a2185c5aced59218c7ccf5c67e2.jpg">
Back Inputs and next state logic.<br><br><img src="paste-b7f3dd92498680d0dc3a9552c5869110b8305375.jpg">
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::05._Finite_State_Machine:_Schematic

Note 231: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
Memory is comprised of locations that can be written to or read from.

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
Memory is comprised of locations that can be written to or read from.

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Text {{c1::Memory}} is comprised of locations that can be written to or read from.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

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ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
n-type transistors are good at pulling down the voltage.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
n-type transistors are good at pulling down the voltage.

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Text <b>n</b>-type transistors are good at pulling {{c1::dow<b>n</b>}}&nbsp;the voltage.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 233: ETH::2. Semester::DDCA

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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
Which types of circuits are the three parts of a FSM?

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
Which types of circuits are the three parts of a FSM?

Sequential Circuits: State register(s)
Combinatorial Circuits: Next state logic, Output logic

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Front Which types of circuits are the three parts of a FSM?
Back Sequential Circuits: State register(s)<br>Combinatorial Circuits: Next state logic, Output logic<br><br><img src="paste-e4af3b21078ddee189e7c5399eb242bb5d90fd10.jpg">
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
To get from voltages to binary values, we can:
  1. Interpret 0V as logical (binary) 0 value
  2. Interpret 3V as logical (binary) 1 value

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
To get from voltages to binary values, we can:
  1. Interpret 0V as logical (binary) 0 value
  2. Interpret 3V as logical (binary) 1 value

In the case of the CMOS NOT Gate we then get:


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Text To get from voltages to binary values, we can:<br><ol><li>{{c1::Interpret 0V as logical (binary) 0 value}}</li><li>{{c2::Interpret 3V as logical (binary) 1 value}}</li></ol>
Extra In the case of the CMOS NOT Gate we then get:<br><br><img src="paste-8bcf6f5a5119256afed57796735aa3578f88b21e.jpg"><br><img src="paste-1ea8562646d826a66676f32131724f1287dda84a.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 235: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
The entire set of unique locations in memory is referred to as the address space.

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory
The entire set of unique locations in memory is referred to as the address space.

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Text The entire set of unique locations in memory is referred to as {{c1::the address space}}.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::15._Memory

Note 236: ETH::2. Semester::DDCA

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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
A clock cycle should be chosen to accommodate the maximum combinational circuit delay.

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
A clock cycle should be chosen to accommodate the maximum combinational circuit delay.

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Text A clock cycle should be chosen to accommodate {{c1::the maximum combinational circuit delay}}.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits

Note 237: ETH::2. Semester::DDCA

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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::12._Basic_Storage_Element:_The_R-S_Latch
Why is \(R=S=0\) illegal in a R-S Latch?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::12._Basic_Storage_Element:_The_R-S_Latch
Why is \(R=S=0\) illegal in a R-S Latch?


If \(R=S=0\), \(Q\) and \(Q'\) will both settle to 1, which breaks our invariant that \(Q \neq Q'\).

If \(S\) and \(R\) transition back to 1 at the same time, \(Q\) and \(Q'\) begin to oscillate between 1 and 0 because their final values depend on each other (metastability).

This eventually settles depending on variation in the circuits (more on this in the Timing Lecture).

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Front Why is&nbsp;\(R=S=0\)&nbsp;illegal in a R-S Latch?<br><br><img src="paste-e939b3a4513b1cd81fee9957735bc8b234d94d58.jpg">
Back <div>If&nbsp;\(R=S=0\),&nbsp;\(Q\)&nbsp;and&nbsp;\(Q'\)&nbsp;will both settle to 1, which <b>breaks</b> our invariant that&nbsp;\(Q \neq Q'\).</div><div><strong><br></strong></div> <div>If&nbsp;\(S\)&nbsp;and&nbsp;\(R\)&nbsp;transition back to 1 at the same time,&nbsp;\(Q\)&nbsp;and&nbsp;\(Q'\)&nbsp;begin to oscillate between 1 and 0 because their final values depend on each other (<strong>metastability</strong>).</div><div><br></div><div>This eventually settles depending on <strong>variation in the circuits</strong> (more on this in the <strong>Timing Lecture</strong>).</div>
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::12._Basic_Storage_Element:_The_R-S_Latch

Note 238: ETH::2. Semester::DDCA

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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
What is this?

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits
What is this?


State diagram of a sequential lock.

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Front What is this?<br><br><img src="paste-8aec0ef28faf022ade42db3b79a541216adc891c.jpg">
Back State diagram of a sequential lock.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::01._Sequential_Logic_Circuits

Note 239: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What's the critical rule for the networks in a CMOS Gate?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What's the critical rule for the networks in a CMOS Gate?


Exactly one network should be ON, and the other network should be OFF at any given time!
  • If both networks are ON at the same time, there is a short circuit → likely incorrect operation.
  • If both networks are OFF at the same time, the output is floating → undefined.

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Front What's the critical rule for the networks in a CMOS Gate?<br><br><img src="paste-73917895a320d3ecb9ef27c6b1a82a66e418278e.jpg">
Back Exactly one network should be ON, and the other network should be OFF at any given time!<br><div><ul><li>If both networks are ON at the same time, there is a <strong>short circuit</strong> → likely incorrect operation.</li><li>If both networks are OFF at the same time, the output is <strong>floating</strong> → undefined.</li></ul></div>
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 240: ETH::2. Semester::DDCA

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ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::06._Finite_State_Machine:_State_Encoding
Output Encoding:
  • Outputs are directly accessible in the state encoding
  • For the traffic light example, since we have 3 outputs (light color), encode state with 3 bits, where each bit represents a color
  • Minimizes output logic
  • Only works for Moore Machines (output function of state)

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::06._Finite_State_Machine:_State_Encoding
Output Encoding:
  • Outputs are directly accessible in the state encoding
  • For the traffic light example, since we have 3 outputs (light color), encode state with 3 bits, where each bit represents a color
  • Minimizes output logic
  • Only works for Moore Machines (output function of state)


Example states: 001, 010, 100, 110
  • Bit₀ encodes green light output
  • Bit₁ encodes yellow light output
  • Bit₂ encodes red light output

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Text <div><div>{{c1::Output}}&nbsp;<strong>Encoding:</strong></div> <ul> <li>Outputs are <strong>directly accessible</strong> in the state encoding</li><li>For the traffic light example, since we have&nbsp;<strong>3 outputs</strong>&nbsp;(light color), encode state with&nbsp;<strong>3 bits</strong>, where each bit represents a color</li><li><strong>Minimizes</strong> {{c2::output logic}}</li><li>Only works for Moore Machines (output function of state)</li></ul></div><br>
Extra <em>Example states:</em>&nbsp;001, 010, 100, 110<br><ul><li>Bit₀ encodes&nbsp;<strong>green</strong>&nbsp;light output</li><li>Bit₁ encodes&nbsp;<strong>yellow</strong>&nbsp;light output</li><li>Bit₂ encodes&nbsp;<strong>red</strong>&nbsp;light output</li></ul>
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::06._Finite_State_Machine:_State_Encoding

Note 241: ETH::2. Semester::DDCA

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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::06._Finite_State_Machine:_State_Encoding
Binary Encoding (Full Encoding):
  • Use the minimum possible number of bits
    • Use log₂(num_states) bits to represent the states
  • Minimizes # flip-flops, but not necessarily output logic or next state logic

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::06._Finite_State_Machine:_State_Encoding
Binary Encoding (Full Encoding):
  • Use the minimum possible number of bits
    • Use log₂(num_states) bits to represent the states
  • Minimizes # flip-flops, but not necessarily output logic or next state logic

Example state encodings: 00, 01, 10, 11

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Text <div>{{c1::Binary Encoding (Full Encoding)}}<strong>:</strong></div> <ul> <li>Use {{c3::the minimum possible number of}} bits <ul> <li>{{c3::Use <em>log₂(num_states)</em> bits to represent the states}}<br></li></ul></li> <li><strong>Minimizes</strong> {{c2::# flip-flops, but not necessarily output logic or next state logic}}</li></ul>
Extra <em>Example state encodings:</em>&nbsp;00, 01, 10, 11
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::06._Finite_State_Machine:_State_Encoding

Note 242: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
What is this?

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
What is this?


A D Flip-Flop.

At the rising edge of clock (clock going from 0\(\rightarrow\)1), Q gets assigned D.
At all other times, Q is unchanged.

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Field Before After
Front What is this?<br><br><img src="paste-3786bddf98da046a8599b4333c56fc1317667876.jpg">
Back A D Flip-Flop.<br><br>At the rising edge of clock (clock going from 0\(\rightarrow\)1), Q gets assigned D.<br>At all other times, Q is unchanged.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 243: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
MOS transistors are imperfect switches.
  • pMOS transistors pass I's well but 0's poorly (holes carry charge).
  • nMOS transistors pass 0's well but I's poorly (electrons carry charge).

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
MOS transistors are imperfect switches.
  • pMOS transistors pass I's well but 0's poorly (holes carry charge).
  • nMOS transistors pass 0's well but I's poorly (electrons carry charge).

This is why AND is built with NAND + NOT.

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Text MOS transistors are imperfect switches.<br><ul><li>pMOS transistors pass {{c1::I}}'s well but {{c1::0}}'s poorly {{c1::(holes carry&nbsp;charge)}}.</li><li>nMOS transistors pass {{c1::0}}'s well but {{c1::I}}'s poorly {{c1::(electrons carry&nbsp;charge)}}.</li></ul>
Extra This is why AND is built with NAND + NOT.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 244: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
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GUID: vw*z~aw+{D
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
Convert this function to canonical form:

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
Convert this function to canonical form:


\(\begin{aligned} F(A,B,C) &= \sum m(3,4,5,6,7) \\ &= m3 + m4 + m5 + m6 + m7 \end{aligned}\)

\(F = \overline{A}BC + A\overline{B}\overline{C} + A\overline{B}C + AB\overline{C} + ABC\)

Note that this isn't minimal form! \(\Rightarrow F = A + BC\)

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Field Before After
Front Convert this function to canonical form:<br><br><img src="paste-e22b6a65df1ec4c9f35c5bf2af9104214c84683f.jpg">
Back \(\begin{aligned} F(A,B,C) &amp;= \sum m(3,4,5,6,7) \\ &amp;= m3 + m4 + m5 + m6 + m7 \end{aligned}\)<br><br>\(F = \overline{A}BC + A\overline{B}\overline{C} + A\overline{B}C + AB\overline{C} + ABC\)<br><br>Note that this isn't minimal form!&nbsp;\(\Rightarrow F = A + BC\)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit

Note 245: ETH::2. Semester::DDCA

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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
How can we use D Latches to implement a FSM?

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
How can we use D Latches to implement a FSM?

We use a D Flip-Flop


When the clock is low, 1st latch propagates D to the input of the 2nd (Q unchanged).

Only when the clock is high, 2nd latch latches D (Q stores D).
At the rising edge of clock (clock going from 0\(\rightarrow\)1), Q gets assigned D.

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Field Before After
Front How can we use D Latches to implement a FSM?
Back We use a D Flip-Flop<br><img src="paste-cc73c8e859236da274b023d8fb58b5b1d90451f3.jpg"><br><br>When the clock is low, 1st latch propagates D to the input of the 2nd (Q unchanged).<br><br>Only when the clock is high, 2nd latch latches D (Q stores D).<br>At the rising edge of clock (clock going from 0\(\rightarrow\)1), Q gets assigned D.
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 246: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Which gate is this?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Which gate is this?


OR

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Front Which gate is this?<br><br><img src="paste-b40d93ca272769316a76dd3bc8a249b2fae10128.jpg">
Back OR<br><br><img src="paste-6e4c2dfe3e807b8506390c3ddfbe974380e318d2.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 247: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
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ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters
What is this?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters
What is this?


Cross-Coupled Inverters.

Has two stable states: \(Q=1\) or \(Q=0\).
Has a third possible "metastable" state with both outputs oscillating between 0 and 1 (we will see this later).

Not useful without a control mechanism for setting Q.

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Field Before After
Front What is this?<br><br><img src="paste-efd9c52b653ff9b4a9524a61121fca9066d0842e.jpg">
Back Cross-Coupled Inverters.<br><br>Has two stable states:&nbsp;\(Q=1\)&nbsp;or&nbsp;\(Q=0\).<br>Has a third possible "metastable" state with both outputs oscillating between 0 and 1 (we will see this later).<br><br>Not useful without a <b>control mechanism </b>for setting Q.<br><br><img src="paste-40fef199fe312874c26dd3080f9b553c5504e4ee.jpg">
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::11._Basic_Element:_Cross-Coupled_Inverters

Note 248: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: w0Wk-s@q$K
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::05._ALU_(Arithmetic_Logic_Unit)
What does an ALU do?

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::05._ALU_(Arithmetic_Logic_Unit)
What does an ALU do?

It combines a variety of arithmetic and logical operations into a single unit (that performs only one function at a time).

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Field-by-field Comparison
Field Before After
Front What does an ALU do?
Back It combines a variety of arithmetic and logical operations into a single unit (that performs only one function at a time).<br><br><img src="paste-d4c76084858a27a2bc15385a19ee00e24b7fc095.jpg">
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::05._ALU_(Arithmetic_Logic_Unit)

Note 249: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: wK&dW+a*q9
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::03._Logical_Completeness
NAND and NOR are logically complete.

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::03._Logical_Completeness
NAND and NOR are logically complete.

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Field-by-field Comparison
Field Before After
Text NAND and NOR are {{c1::logically complete}}.
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::03._Logical_Completeness

Note 250: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: wfjJW35xJe
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Which gate is this?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
Which gate is this?


Buffer

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Field-by-field Comparison
Field Before After
Front Which gate is this?<br><br><img src="paste-ec6272f8168e59f9e10c0a00d75245c19c05bf8d.jpg">
Back Buffer<br><br><img src="paste-a84f4ec12787c4f030593835d9c2ce773bf394d6.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 251: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: x!EU,iyr5{
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
A FSM consists of these elements:
  1. A finite number of states
  2. A finite number of external inputs
  3. A finite number of external outputs
  4. An explicit specification of all state transitions
  5. An explicit specification of what determines each external output value

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
A FSM consists of these elements:
  1. A finite number of states
  2. A finite number of external inputs
  3. A finite number of external outputs
  4. An explicit specification of all state transitions
  5. An explicit specification of what determines each external output value

State: snapshot of all relevant elements of the system at the time of the snapshot

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Field-by-field Comparison
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Text A FSM consists of these elements:<br><ol><li>{{c1::A finite number of states}}</li><li>{{c2::A finite number of external inputs}}<br></li><li>{{c2::A finite number of external outputs}}</li><li>{{c3::An explicit specification of all state transitions}}</li><li>{{c4::An explicit specification of what determines each external output value}}<br></li></ol>
Extra State: snapshot of all relevant elements of the system at the time of the snapshot
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 252: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: x,YN;U)u48
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What's the formula for static power consumption?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
What's the formula for static power consumption?

\(V\cdot I_\text{leakage}\)

(supply voltage * leakage current)

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Field-by-field Comparison
Field Before After
Front What's the formula for static power consumption?
Back \(V\cdot I_\text{leakage}\)<br><br>(supply voltage * leakage current)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 253: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: xJUzR))XQ)
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
When transistors are in parallel, the network is ON if one of the transistors is ON.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
When transistors are in parallel, the network is ON if one of the transistors is ON.

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Field-by-field Comparison
Field Before After
Text When transistors are in parallel, the network is ON if {{c1::one of the transistors is ON}}.
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates

Note 254: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Occlusio
GUID: y!>GF#oDFU
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::04._Finite_State_Machine:_Output_Table
Determine the SOP of \(L_{A1}\) from this output table:
image-occlusion:rect:left=.1448:top=.7889:width=.1955:height=.0794:oi=1

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::04._Finite_State_Machine:_Output_Table
Determine the SOP of \(L_{A1}\) from this output table:
image-occlusion:rect:left=.1448:top=.7889:width=.1955:height=.0794:oi=1

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Field Before After
Occlusion {{c1::image-occlusion:rect:left=.1448:top=.7889:width=.1955:height=.0794:oi=1}}<br>
Image <img src="paste-2104652c4307f2325008cef16a8a906d2b837817.jpg">
Header Determine the SOP of&nbsp;\(L_{A1}\)&nbsp;from this output table:
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::04._Finite_State_Machine:_Output_Table

Note 255: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: y$t0Kq)TQh
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::1._Decoder
The decoder is useful in determining how to interpret a bit pattern.

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::1._Decoder
The decoder is useful in determining how to interpret a bit pattern.

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Field-by-field Comparison
Field Before After
Text The {{c1::decoder}} is useful in determining how to interpret a bit pattern.
Extra <img src="paste-1ce8f7a9f880338a7d797182beb4be144fe192e6.jpg">
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::6._Combinational_Building_Blocks_used_in_Modern_Computers::1._Decoder

Note 256: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: y2>qnHc%Pf
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
Why can't we simply wire a clock to WE of a D Latch to implement a FSM?

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
Why can't we simply wire a clock to WE of a D Latch to implement a FSM?


Whenever the clock is high, the latch propagates D to Q.
The latch is "transparent".

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Field-by-field Comparison
Field Before After
Front Why can't we simply wire a clock to WE of a D Latch to implement a FSM?<br><br><img src="paste-efb7af3e85cc5c79a9c81bbd59733d3e8ab3a4d2.jpg">
Back Whenever the clock is high, the latch propagates D to Q.<br>The latch is "transparent".<br><br><img src="paste-4414073a5709ca8e5710a64953abd1a4140c689c.jpg">
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 257: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Occlusio
GUID: y6L!`3rg+h
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::17._Sequential_Logic_Circuits
What's the difference between these two?
image-occlusion:rect:left=.0066:top=.7908:width=.9822:height=.1903

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::17._Sequential_Logic_Circuits
What's the difference between these two?
image-occlusion:rect:left=.0066:top=.7908:width=.9822:height=.1903

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Occlusion {{c1::image-occlusion:rect:left=.0066:top=.7908:width=.9822:height=.1903}}<br>
Image <img src="paste-56ccd7a0fecaeb262dc5922a407d2ee8a4c16d37.jpg">
Header What's the difference between these two?
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::17._Sequential_Logic_Circuits

Note 258: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: yixUKU?m~)
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Front

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
Essence of Simplification (Uniting Theorem)

Find two-element subsets of the ON-set where only one variable changes its value. This single varying variable can be eliminated!

Back

ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules
Essence of Simplification (Uniting Theorem)

Find two-element subsets of the ON-set where only one variable changes its value. This single varying variable can be eliminated!

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Field-by-field Comparison
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Text Essence of Simplification (Uniting Theorem)<br><br>Find two-element subsets of the ON-set where only one variable changes its value. This single varying variable can be {{c1::eliminated}}!
Tags: ETH::2._Semester::DDCA::03._Combinational_Logic_II_and_Sequential_Logic::07._Logic_Simplification_using_Boolean_Algebra_Rules

Note 259: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: zh6Oh%kTi<
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Front

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
How does a rising-clock-edge triggered Flip-Flop work?



Two inputs: CLK, D

Function:
  1. The flip-flop "samples" D on the rising edge of CLK (positive edge)
  2. When CLK rises from 0 to 1, D passes through to Q
  3. Otherwise, Q holds its previous value
  4. Q changes only on the rising edge of CLK

Back

ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines
How does a rising-clock-edge triggered Flip-Flop work?



Two inputs: CLK, D

Function:
  1. The flip-flop "samples" D on the rising edge of CLK (positive edge)
  2. When CLK rises from 0 to 1, D passes through to Q
  3. Otherwise, Q holds its previous value
  4. Q changes only on the rising edge of CLK

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Field-by-field Comparison
Field Before After
Text How does a rising-clock-edge triggered Flip-Flop work?<br><br><img src="paste-967b8524a938dc72302521297e9b9c8e8f17928c.jpg"><br><br>Two inputs: CLK, D<br><br>Function:<br><ol><li>The flip-flop "samples" D on {{c1::the rising edge of CLK (positive edge)}}</li><li>When CLK rises from 0 to 1, D {{c2::passes through to Q}}</li><li>Otherwise, {{c2::Q holds its previous value}}</li><li>Q changes only on {{c3::the rising edge of CLK}}</li></ol>
Tags: ETH::2._Semester::DDCA::04a._Sequential_Logic_Design_II_&_Finite_State_Machines::02._Finite_State_Machines

Note 260: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Classic
GUID: {Na1}u5VN
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Front

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
How can we convert from Minterm to Maxterm?

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
How can we convert from Minterm to Maxterm?

  1. Rewrite minterm shorthand using maxterm shorthand
  2. Replace minterm indices with the indices not already used
E.g., \(F(A,B,C) = \sum m(3,4,5,6,7) = \prod M(0,1,2)\)

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Field-by-field Comparison
Field Before After
Front How can we convert from Minterm to Maxterm?
Back <ol><li>Rewrite minterm shorthand using maxterm shorthand</li><li>Replace minterm indices with the indices not already used</li></ol>E.g.,&nbsp;\(F(A,B,C) = \sum m(3,4,5,6,7) = \prod M(0,1,2)\)
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::5._Using_Boolean_Equations_to_Represent_a_Logic_Circuit
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