Anki Deck Changes

Commit: c1f22510 - 🔧

Author: lhorva <lhorva@student.ethz.ch>

Date: 2026-03-19T01:45:35+01:00

Changes: 3 note(s) changed (0 added, 3 modified, 0 deleted)

ℹ️ Cosmetic Changes Hidden: 1 note(s) had formatting-only changes and are not shown below • 1 HTML formatting changes

Note 1: ETH::2. Semester::A&W

Deck: ETH::2. Semester::A&W
Note Type: Horvath Occlusio
GUID: w,M||$B!bf
modified

Before

Front

ETH::2._Semester::A&W::1._Graphentheorie::5._Kreise::2._Hamiltonkreise
Hamiltonkreise mit DP
image-occlusion:rect:left=.0549:top=.1775:width=.9042:height=.1202
image-occlusion:rect:left=.0813:top=.4818:width=.8976:height=.407
image-occlusion:rect:left=.1588:top=.8926:width=.7186:height=.0736

Back

ETH::2._Semester::A&W::1._Graphentheorie::5._Kreise::2._Hamiltonkreise
Hamiltonkreise mit DP
image-occlusion:rect:left=.0549:top=.1775:width=.9042:height=.1202
image-occlusion:rect:left=.0813:top=.4818:width=.8976:height=.407
image-occlusion:rect:left=.1588:top=.8926:width=.7186:height=.0736

After

Front

ETH::2._Semester::A&W::1._Graphentheorie::5._Kreise::2._Hamiltonkreise
Hamiltonkreise mit DP
image-occlusion:rect:left=.1591:top=.8923:width=.7185:height=.0742
image-occlusion:rect:left=.3252:top=.7428:width=.5272:height=.0923
image-occlusion:rect:left=.0549:top=.1782:width=.9041:height=.1203
image-occlusion:rect:left=.1645:top=.4824:width=.1234:height=.0878
image-occlusion:rect:left=.2518:top=.5747:width=.3462:height=.0744

Back

ETH::2._Semester::A&W::1._Graphentheorie::5._Kreise::2._Hamiltonkreise
Hamiltonkreise mit DP
image-occlusion:rect:left=.1591:top=.8923:width=.7185:height=.0742
image-occlusion:rect:left=.3252:top=.7428:width=.5272:height=.0923
image-occlusion:rect:left=.0549:top=.1782:width=.9041:height=.1203
image-occlusion:rect:left=.1645:top=.4824:width=.1234:height=.0878
image-occlusion:rect:left=.2518:top=.5747:width=.3462:height=.0744
Field-by-field Comparison
Field Before After
Occlusion {{c1::image-occlusion:rect:left=.0549:top=.1775:width=.9042:height=.1202}}<br>{{c2::image-occlusion:rect:left=.0813:top=.4818:width=.8976:height=.407}}<br>{{c3::image-occlusion:rect:left=.1588:top=.8926:width=.7186:height=.0736}}<br> {{c3::image-occlusion:rect:left=.1591:top=.8923:width=.7185:height=.0742}}<br>{{c2::image-occlusion:rect:left=.3252:top=.7428:width=.5272:height=.0923}}<br>{{c1::image-occlusion:rect:left=.0549:top=.1782:width=.9041:height=.1203}}<br>{{c4::image-occlusion:rect:left=.1645:top=.4824:width=.1234:height=.0878}}<br>{{c5::image-occlusion:rect:left=.2518:top=.5747:width=.3462:height=.0744}}<br>
Tags: ETH::2._Semester::A&W::1._Graphentheorie::5._Kreise::2._Hamiltonkreise

Note 2: ETH::2. Semester::DDCA

Deck: ETH::2. Semester::DDCA
Note Type: Horvath Cloze
GUID: vK&i;bo$O;
modified

Before

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
MOS transistors are imperfect switches.
  • pMOS transistors pass I's well but 0's poorly (holes carry charge).
  • nMOS transistors pass 0's well but I's poorly (electrons carry charge).

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
MOS transistors are imperfect switches.
  • pMOS transistors pass I's well but 0's poorly (holes carry charge).
  • nMOS transistors pass 0's well but I's poorly (electrons carry charge).
This is why AND is built with NAND + NOT.

After

Front

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
MOS transistors are imperfect switches.
  • pMOS transistors pass I's well but 's poorly (holes carry charge).
  • nMOS transistors pass 0's well but I's poorly (electrons carry charge).

Back

ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
MOS transistors are imperfect switches.
  • pMOS transistors pass I's well but 's poorly (holes carry charge).
  • nMOS transistors pass 0's well but I's poorly (electrons carry charge).
This is why AND is built with NAND + NOT.
Field-by-field Comparison
Field Before After
Text MOS transistors are imperfect switches.<br><ul><li>pMOS transistors pass {{c1::I}}'s well but {{c1::0}}'s poorly {{c1::(holes carry&nbsp;charge)}}.</li><li>nMOS transistors pass {{c1::0}}'s well but {{c1::I}}'s poorly {{c1::(electrons carry&nbsp;charge)}}.</li></ul> MOS transistors are imperfect switches.<br><ul><li>pMOS transistors pass {{c1::I}}'s well but {{c10}}'s poorly {{c1::(holes carry&nbsp;charge)}}.</li><li>nMOS transistors pass {{c1::0}}'s well but {{c1::I}}'s poorly {{c1::(electrons carry&nbsp;charge)}}.</li></ul>
Tags: ETH::2._Semester::DDCA::02._Combinational_Logic::2._Logic_Gates
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